PI2EQX5804CNJE Datasheet, PDF (15/23 Pages) Pericom Semiconductor Corporation – 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis

PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
(3) Output Emphasis Configuration earlier in this document for setting information. All four A channels get
the same configuration settings.
BYTE 9 - B-Channels Equalizer and Output Control (BEOC)
SELx_B: Equalizer configuration,
Dx_B: Emphasis control,
Sx_B: Output level control (see Configuration Table)
Bit
7
6
5
4
3
Name
SEL0_B SEL1_B SEL2_B
D0_B
D1_B
Type
R/W
R/W
R/W
R/W
R/W
Power-on
State
SEL0_B
SEL1_B
SEL2_B
D0_B
D1_B
2
D2_B
R/W
D2_B
1
S0_B
R/W
S0_B
0
S1_B
R/W
S1_B
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The B-Channels Equalizer and Output Control register is used to control the configuration of the input equal-
izer and output emphasis and levels of the four B channels. These register bits are loaded from the input con-
figuration pins of the same name at power-on. These bits may be changed if the MODE# input is set to allow
I²C configuration. Please refer to the tables (1) Equalizer Configuration, (2) Output Swing Configuration and
(3) Output Emphasis Configuration earlier in this document for setting information. All four B channels get
the same configuration settings.
BYTE 10 - Reserved
BYTE 11 - Reserved
Reserved Bytes 10 and 11 are also visible via the I²C interface. These bytes are R/W, are initialized to 0 at
power up, are used for IC manufacturing test purposes and should not be changed for normal operation.
Start & Stop Conditions
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. A LOW to
HIGH transition on the SDA line while SCL is HIGH defines a STOP condition, as shown in the figure below.
09-0001
I ²C
15
PS8926B
06/08/09