PI2EQX5804CNJE Datasheet, PDF (11/23 Pages) Pericom Semiconductor Corporation – 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis

PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Transferring Data
Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge
bit. Data is transferred with the most significant bit (MSB) first (see the I²C Data Transfer diagram). The
PI2EQX5804C will never hold the clock line SCL LOW to force the master into a wait state.
Note: Byte-write and byte-read transfers have a fixed offset of 0x00, because of the very small number of con-
figuration bytes. An offset byte presented by a host to the PI2EQX5804C is not used.
Addressing
Up to eight PI2EQX5804C devices can be connected to a single I²C bus. The PI2EQX5804C supports 7-bit
addressing, with the LSB indicating either a read or write operation. The address for a specific device is deter-
mined by the A0, A1 and A4 input pins.
Address Assignment
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
Program
0
0
Programmable
1=R, 0=W
Acknowledge
Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH)
during the acknowledge clock pulse, the PI2EQX5804C will pull down the SDA line during the acknowledge
clock pulse so that it remains stable LOW during the HIGH period of this clock pulse as indicated in the I²C
Data Transfer diagram. The PI2EQX5804C will generate an acknowledge after each byte has been received.
Data Transfer
A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, the PI2EQX5804C
will watch the next byte of information for a match with its address setting. When a match is found it will
respond with a read or write of data on the following clocks. Each byte must be followed by an acknowledge
bit, except for the last byte of a read cycle which ends with a stop bit. For a write cycle, the first data byte fol-
lowing the address byte is a dummy or fill byte that is not used by the PI2EQX5804C. This byte is provided
to provided compatibility with systems implementing 10-bit addressing. Data is transferred with the most
significant bit (MSB) first. After each block write, address pointer will reset to byte 0.
09-0001
11
PS8926B
06/08/09