PI2EQX5804CNJE Datasheet, PDF (14/23 Pages) Pericom Semiconductor Corporation – 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis

PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
BYTE 6 - Power Down Control (PWR)
PD_xy# =0=channel off/power down, PD_xy# =1=normal operation, Latch from PD# input at startup
Bit
7
6
5
4
3
2
Name
PD_A0# PD_B0# PD_A1# PD_B1# PD_A2# PD_B2#
Type
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
PD#
PD#
PD#
PD#
PD#
PD#
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
1
PD_A3#
R/W
PD#
0
PD_B3#
R/W
PD#
The Power Down Control register allows for individual control over each channel for power savings. When
PD_xy# is logic 0 the channel is turned off. When PD_xy# is 1 then the channel is enabled for normal
operation.
BYTE 7 - Receiver Detect Enable (RXD)
RXD_xy =0=channel off/power down, RXD_xy =1=normal operation, Latch from PD# input at startup
Bit
7
6
5
4
3
2
Name
RXD_A0 RXD_B0 RXD_A1 RXD_B1 RXD_A2 RXD_B2
Type
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
1
RXD_A3
R/W
RXD_A
0
RXD_B3
R/W
RXD_B
The Receiver Detect Enable register allows for control of the receiver detect state machine for each individual
channel. When RXD_xy is set to 0, then the receiver detect function is disabled. When RXD_xy is logic 1,
then the receiver detect state machine is enabled for operation. The initial state of the register bits are deter-
mined by the RXD_A and RXD_B input pins during power-up.
BYTE 8 - A-Channels Equalizer and Output Control (AEOC)
SELx_A: Equalizer configuration, Dx_A: Emphasis control, Sx_A: Output level control (see Configuration Table)
Bit
7
6
5
4
3
2
Name
SEL0_A SEL1_A SEL2_A
D0_A
D1_A
D2_A
Type
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
SEL0_A
SEL1_A
SEL2_A
D0_A
D1_A
D2_A
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
1
S0_A
R/W
S0_A
0
S1_A
R/W
S1_A
The A-Channels Equalizer and Output Control register is used to control the configuration of the input equal-
izer and output emphasis and levels of the four A channels. These register bits are loaded from the input con-
figuration pins of the same name at power-on. These bits may be changed if the MODE# input is set to allow
I²C configuration. Please refer to the tables (1) Equalizer Configuration, (2) Output Swing Configuration and
09-0001
14
PS8926B
06/08/09