PI2EQX5804CNJE Datasheet, PDF (12/23 Pages) Pericom Semiconductor Corporation – 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis

PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Register Description
Byte 0 - Signal Detect (SIG)
SIG_xy=0=low input signal, SIG_xy=1=valid input signal
Bit
Name
7
SIG_A0
6
SIG_B0
5
SIG_A1
4
SIG_B1
3
SIG_A2
2
SIG_B2
Type
R
R
R
R
R
R
Power-on
X
X
X
X
X
X
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
1
SIG_A3
R
X
0
SIG_B3
R
X
The Signal Detect register provides information on the instantaneous status of the channel input from the Input Level
Threshold Detect circuit. If the input level falls below the Vth- level the relevant SIG_xy bit will be 0, indicating a low-
level noise or electrical idle input, resulting in the outputs going to the high-impedance off state or squelch mode. If the
input level is above Vth-, then SIG_xy is 1, indicating a valid input signal, and active signal recovery operation.
Byte 1 - Receiver Detect Output Register (RX50)
LB_xyxy#=0=loopback mode, LB_xyxy#=1=normal mode, DE_x=0=pre-emphasis, DE_x=1=de-emphasis
Bit
7
6
5
4
3
2
Name RX50_A0 RX50_B0 RX50_A1 RX50_B1 RX50_A2 RX50_B2
Type
R
R
R
R
R
R
Power-on
X
X
X
X
X
X
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
1
RX50_A3
R
X
0
RX50_B3
R
X
The RX50_xy bits report the result of a receiver detection cycle. One bit is assigned for each channel of the device.
RX50_xy is at a logic 1 level indicating a load and receiver was detected. When RX50_xy is 0 then a load device was
not detected. The RX50 register is read-only, and is undefined after power-up until a Receiver Detection cycle com-
pletes.
Byte 2 - Loopback and Emphasis Control Register (LBEC)
LB_xyxy#=0=loopback mode, LB_xyxy#=1=normal mode, DE_x=0=pre-emphasis, DE_x=1=de-emphasis
Bit
7
6
5
4
3
2
1
0
Name LB_A0B0# LB_A1B1# LB_A2B2# LB_A3B3# DE_A
DE_B
rsvd
rsvd
Type
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Power-on
LB#
LB#
LB#
LB#
DE_A
DE_B
X
X
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
Individual control for each lane is provided for the loopback function via this register.
09-0001
12
PS8926B
06/08/09