PI2EQX5804CNJE Datasheet, PDF (1/23 Pages) Pericom Semiconductor Corporation – 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis

PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™
with Equalization & Emphasis
Features
• Up to 5.0Gbps PCIe® 2.0 Serial ReDriver™
• Supporting 8 differential channels or 4 lanes of PCIe Interface
• Pin strapped and I²C configuration controls
• Adjustable receiver equalization
• Adjustable transmitter amplitude and de-emphasis
• Variable input an output termination
• 1:2 channel broadcast
• Channel loop-back
• Electrical Idle fully supported
• Receiver detect and individual output control
• Single supply voltage, 1.2V ± 0.05V
• Power down modes
• Packaging: 100-contact LBGA, Pb-free & Green
Description
Pericom Semiconductor’s PI2EQX5804C is a low power, PCIe®
compliant signal ReDriver™. The device provides programmable
equalization, amplification, and de-emphasis by using 8 select
bits, to optimize performance over a variety of physical mediums
by reducing Inter-symbol interference.
PI2EQX5804C supports eight 100-Ohm Differential CML
data I/O’s between the Protocol ASIC to a switch fabric, across
a backplane, or extends the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the PCIe signal before the ReDriver, whereas
the integrated de-emphasis circuitry provides flexibility with
signal integrity of the signal after the ReDriver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX5804C also provides power management Stand-by mode
operated by a Power Down pin.
Block Diagram
xyRx+
xyRx-
xyTx+
xyTx-
+
−
+
− _Equalizer
Input level detect
to control logic
Output
Controls
+
−
xyTx+
xyTx-
+
−
Output
Controls
A
B
Input level detect
to control logic
Equalizer
+
−
+
−
Data Lane Repeats 4 Times
xyRx+
xyRx-
SELy_x
Sy_x
Dy_x
DE_x
PD#
SDA
SCL
Control registers
& logic
Power
Management
I²C Control
Mode
LB#
RXD_x
RES_x
Ax
Pin Configuration (Top-Side View)
1
2
3
4
5
6
7
8
9
10
A ^VDD B0TX- B0TX+ ^{VDD SCL SDA VDD B0RX+ B0RX- VDD}
B A1RX+ _{GND GND A0RX - DE_A} VDD A0TX- GND GND A1TX+
C A1RX- GND GND A0RX+ NC PD# ^{A0TX+ GND GND A1TX-}
D VDD B1TX+ B1TX- _VDD D2_A NC VDD B1RX- B1RX+ VDD
E SEL0_A SEL1_A SEL2_A D0_A D1_A S0_A ^{RXD_A S1_A SIG_A RX50_A}
F RX50_B SIG_B S1_B RXD_B S0_B A1 ^{SEL2_B LB# SEL1_B SEL0_B}
G VDD A2RX- A2RX+ VDD MODE D0_B ^{VDD A2TX+ A2TX - VDD}
H B2TX+ GND GND B3TX- DE_B A0 ^{B3RX- GND GND B2RX+}
J B2TX- GND GND B3TX+ RESET# D1_B ^{B3RX+ GND GND B2RX-}
K VDD A3RX+ A3RX- VDD D2_B A4
VDD A3TX- A3TX+ VDD
09-0001
1
PS8926B
06/08/09