PI2EQX5804CNJE Datasheet, PDF (5/23 Pages) Pericom Semiconductor Corporation – 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis

PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Equalizer Configuration
The PI2EQX5804C input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) re-
sulting from long signal traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high-
frequency signal components. Because either too little, or too much, signal compensation may be non-optimal
eight levels are provided to adjust for any application.
Equalizer configuration is performed in two ways determined by the state of the MODE pin. When the device
first powers up, the SELx_[A:B] input pins are read into the appropriate control registers to set the equalization
characteristic. If the MODE pin is low, reprogramming of these control registers via I²C is allowed.
Each group of four channels, A and B, has separate equalization control, and all four channels within the group
are assigned the same configuration state. The Equalizer Selection table below describes pin strapping options
and associated operation of the equalizer. Refer to the section on I²C programming for information on soft-
ware configuration of the equalizer.
Equalizer Selection
SEL2_[A:B]
0
0
0
0
1
1
1
1
SEL1_[A:B]
0
0
1
1
0
0
1
1
SEL0_[A:B]
0
1
0
1
0
1
0
1
@1.25GHz
0.5dB
0.6dB
1.0dB
1.9dB
2.8dB
3.6dB
5.0dB
7.7dB
@2.5GHz
1.2dB
1.5dB
2.6dB
4.3dB
5.8dB
7.1dB
9.0dB
12.3dB
Output Configuration
The PI2EQX5804C provides flexible output strength and emphasis controls to provide the optimum signal to
pre-compensate for losses across long trace or noisy environments so that the receiver gets a clean eye open-
ing. Control of output configuration is grouped for the A and B channels, so that each channel within the
group has the same setting.
Output configuration is performed in two ways depending on the state of the MODE pin. When the device
first powers up, the Sx_[A:B], and Dx_[A:B] input pins are read into the appropriate control registers to set the
power-on state. If the MODE pin is low, reprogramming of these control registers via I²C is allowed.
The Output Swing Control table shows available configuration settings for output level control, as specified
using the Sx_y pins and registers.
09-0001
5
PS8926B
06/08/09