English
Language : 

AR0135CS Datasheet, PDF (9/27 Pages) ON Semiconductor – 1/3‐inch 1.2 Mp CMOS Digital Image Sensor
AR0135CS
Table 3. PIN DESCRIPTIONS − 63-BALL IBGA PACKAGE (continued)
Name
IBGA Pin
Type
Description
SLVSC_P
B3
Output HiSPi serial DDR clock differential P
SLVS2_N
B4
Output HiSPi serial data, lane 2, differential N
SLVS2_P
B5
Output HiSPi serial data, lane 2, differential P
VAA
EXTCLK
B7, B8
C1
Power
Input
Analog power
External input clock
VDD_SLVS
C2
Power HiSPi power (may leave unconnected if parallel interface is
used)
SLVS3_N
C3
Output (Unsupported) HiSPi serial data, lane 3, differential N
SLVS3_P
C4
Output (Unsupported) HiSPi serial data, lane 3, differential P
DGND
VDD
AGND
SADDR
SCLK
SDATA
VAA_PIX
LINE_VALID
FRAME_VALID
PIXCLK
FLASH
C5, D4, D5, E5, F5, G5, H5
A6, A7, B6, C6, D6
C7, C8
D1
D2
D3
D7, D8
E1
E2
E3
E4
Power
Power
Power
Input
Input
I/O
Power
Output
Output
Output
Output
Digital GND
Digital power
Analog GND
Two-wire serial address select
Two-wire serial clock input
Two-wire serial data I/O
Pixel power
Asserted when DOUT line data is valid
Asserted when DOUT frame data is valid
Pixel clock out. DOUT is valid on rising edge of this clock
Control signal to drive external light sources
VDD_IO
DOUT8
DOUT9
DOUT10
DOUT11
TEST
DOUT4
DOUT5
DOUT6
DOUT7
TRIGGER
E6, F6, G6, H6, H7
F1
F2
F3
F4
F7
G1
G2
G3
G4
G7
Power
Output
Output
Output
Output
Input
Output
Output
Output
Output
Input
I/O supply power
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output (MSB)
Manufacturing test enable pin (connect to DGND)
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output
Exposure synchronization input. (Connect to DGND if HiSPi
interface is used)
OE_BAR
G8
Input
Output enable (active LOW)
DOUT0
H1
Output Parallel pixel data output (LSB)
DOUT1
H2
Output Parallel pixel data output
DOUT2
H3
Output Parallel pixel data output
DOUT3
H4
Output Parallel pixel data output
RESET_BAR
H8
Input
Asynchronous reset (active LOW). All settings are restored to
factory default
Reserved
E7, E8, F8
N/A
Reserved (do not connect)
www.onsemi.com
9