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AR0135CS Datasheet, PDF (13/27 Pages) ON Semiconductor – 1/3‐inch 1.2 Mp CMOS Digital Image Sensor
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AR0135CS
ELECTRICAL SPECIFICATIONS
Unless otherwise stated, the following specifications
apply to the following conditions:
VDD = 1.8 V –0.10/+0.15; VDD_IO = VDD_PLL = VAA =
VAA_PIX = 2.8 V ±0.30;
VDD_SLVS = 0.4 V –0.1/+0.2; TA = −30°C to +70°C; output
load = 10 pF;
PIXCLK frequency = 74.25 MHz; HiSPi off.
Two-Wire Serial Register Interface
The electrical characteristics of the two-wire serial
register interface (SCLK, SDATA) are shown in Figure 14 and
Table 4.
SDATA
tf
tLOW
tr
tSU;DAT
tf
tHD;STA
tr
tBUF
SCLK
tHD;STA
S
tHD;DAT
tHIGH
tSU;STA
Sr
tSU;STO
P
S
NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued.
Figure 14. Two-Wire Serial Bus Timing Parameters
Table 4. TWO-WIRE SERIAL BUS CHARACTERISTICS
(fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; VDD_DAC = 2.8 V; TA = 25°C)
Standard Mode
Fast-Mode
Parameter
Symbol
Min
Max
Min
Max
Unit
SCLK Clock Frequency
tSCL
0
100
0
400
kHz
Hold Time (Repeated) START
Condition
After this Period, the First Clock
tHD;STA
4.0
−
0.6
−
ms
Pulse is Generated
LOW Period of the SCLK Clock
tLOW
4.7
−
1.3
−
ms
HIGH Period of the SCLK Clock
tHIGH
4.0
−
0.6
−
ms
Set-up Time for a Repeated
tSU;STA
4.7
−
0.6
−
ms
START Condition
Data Hold Time
Data Set-up Time
Rise Time of both SDATA and
SCLK Signals
Fall Time of both SDATA and SCLK
Signals
tHD;DAT
tSU;DAT
tr
tf
0 (Note 4)
250
−
−
3.45 (Note 5)
−
1000
300
0 (Note 6)
100 (Note 6)
20 + 0.1Cb
(Note 7)
20 + 0.1Cb
(Note 7)
0.9 (Note 5)
ms
−
ns
300
ns
300
ns
Set-up Time for STOP Condition
tSU;STO
4.0
−
0.6
−
ms
Bus Free Time between a STOP
tBUF
4.7
−
1.3
−
ms
and START Condition
Capacitive Load for each Bus Line
Cb
−
400
−
400
pF
Serial Interface Input Pin
CIN_SI
−
3.3
−
3.3
pF
Capacitance
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