AR0135CS Datasheet, PDF (14/27 Pages) ON Semiconductor – 1/3‐inch 1.2 Mp CMOS Digital Image Sensor

AR0135CS
Table 4. TWO-WIRE SERIAL BUS CHARACTERISTICS (continued)
(f_EXTCLK = 27 MHz; V_DD = 1.8 V; V_DD_IO = 2.8 V; V_AA = 2.8 V; V_AA_PIX = 2.8 V; V_DD_PLL = 2.8 V; V_DD_DAC = 2.8 V; T_A = 25°C)
Standard Mode
Fast-Mode
Parameter
Symbol
Min
Max
Min
Max
Unit
S_DATA Max Load Capacitance
CLOAD_SD
−
30
−
30
pF
S_DATA Pull-up Resistor
RSD
1.5
4.7
1.5
4.7
kW
1. This table is based on I²C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I²C-compatible.
3. All values referred to V_IHmin = 0.9 V_DD_IO and V_ILmax = 0.1 V_DD_IO levels. Sensor EXCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the S_DATA signal to bridge the undefined region of the falling edge of S_CLK.
5. The maximum t_HD;DAT has only to be met if the device does not stretch the LOW period (t_LOW) of the S_CLK signal.
6. A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement t_SU;DAT 250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the S_CLK signal. If such a device does stretch the LOW period
of the S_CLK signal, it must output the next data bit to the S_DATA line t_r max + t_SU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode
I²C-bus specification) before the S_CLK line is released.
7. Cb = total capacitance of one bus line in pF.
I/O Timing
By default, the AR0135CS launches pixel data, FV and
LV with the falling edge of PIXCLK. The expectation is that
the user captures D_OUT[11:0], FV and LV using the rising
edge of PIXCLK. The launch edge of PIXCLK can be
configured in register R0x3028. See Figure 15 and Table 5
for I/O timing (AC) characteristics.
t_R
t_F
t_RP
t_FP
EXTCLK
t_EXTCLK
90%
10%
90%
10%
90%
10%
90%
10%
PIXCLK
Data[11:0]
LINE_VALID/
FRAME_VALID
t_PD
Pxl_0
Pxl_1
Pxl_2
Pxl_n
t_PLH
t_PFH
FRAME_VALID Leads LINE_VALID
by 6 PIXCLKs
t_PFL
t_PLL
FRAME_VALID Trails LINE_VALID
by 6 PIXCLKs
Figure 15. I/O Timing Diagram
Table 5. I/O TIMING CHARACTERISTICS, PARALLEL OUTPUT (1.8 V V_DD_IO) (Note 1)
Symbol
Definition
Condition
Min
Typ
f_EXTCLK Input Clock Frequency
6
−
t_EXTCLK Input Clock Period
20
−
t_R
Input Clock Rise Time PLL Enabled
−
3
t_F
Input Clock Fall Time
PLL Enabled
−
3
t_jJITTER Input Clock Jitter
−
−
t_cp
EXTCLK to PIXCLK
Nominal Voltages, PLL Disabled, PIXCLK Slew
5.7
−
Propagation Delay
Rate = 4
t_RP
PIXCLK Rise Time
t_FP
PIXCLK Fall Time
PIXCLK Duty Cycle
PCLK Slew Rate = 6
PCLK Slew Rate = 6
1.3
−
1.3
−
40
50
f_PIXCLK PIXCLK Frequency
PIXCLK Slew Rate = 6, Data Slew Rate = 7
6
−
t_PD
PIXCLK to Data Valid
PIXCLK Slew Rate = 6, Data Slew Rate = 7
−2.5
−
Max
50
166
−
−
600
14.3
4.0
3.9
60
74.25
2
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
%
MHz
ns
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