AR0135CS Datasheet, PDF (18/27 Pages) ON Semiconductor – 1/3‐inch 1.2 Mp CMOS Digital Image Sensor

AR0135CS
Table 14. OPERATING CURRENT CONSUMPTION FOR HiSPi OUTPUT
(V_AA = V_AA_PIX = V_DD_IO = V_DD_PLL = 2.8 V; V_DD = 1.8 V; PLL Enabled and PIXCLK = 74.25 MHz; T_A = 25°C; C_LOAD = 10 pF)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
I_DD
Digital Operating Current
HiSPi, Streaming, Full Resolution 54 fps
−
70
90
mA
I_DD_IO I/O Digital Operating Current HiSPi, Streaming, Full Resolution 54 fps
−
0.2
1
mA
I_AA
Analog Operating Current
HiSPi, Streaming, Full Resolution 54 fps
−
40
55
mA
I_AA_PIX Pixel Supply Current
HiSPi, Streaming, Full Resolution 54 fps
−
7
9
mA
I_DD_PLL PLL Supply Current
HiSPi, Streaming, Full Resolution 54 fps
−
11
14
mA
I_DD_SLVS HiSPi Supply Current
HiSPi, Streaming, Full Resolution 54 fps
−
9
12
mA
Table 15. STANDBY CURRENT CONSUMPTION
(Analog − V_AA + V_AA_PIX + V_DD_PLL; Digital − V_DD + V_DD_IO; T_A = 25°C)
Definition
Condition
Min
Typ
Max
Unit
Hard Standby (Clock OFF, Driven Low)
Analog, 2.8 V
–
3
15
mA
Digital, 1.8 V
–
25
125
mA
Hard Standby (Clock ON, EXTCLK = 20 MHz)
Analog, 2.8 V
–
12
25
mA
Digital, 1.8 V
–
1.1
1.7
mA
Soft Standby (Clock OFF, Driven Low)
Analog, 2.8 V
–
3
15
mA
Digital, 1.8 V
–
25
125
mA
Soft Standby (Clock ON, EXTCLK = 20 MHz)
Analog, 2.8 V
–
12
25
mA
Digital, 1.8 V
–
1.1
1.7
mA
HiSPi Electrical Specifications
The ON Semiconductor AR0135CS sensor supports
SLVS mode only, and does not have a DLL for timing
adjustments. Refer to the High-Speed Serial Pixel (HiSPi)
Interface Physical Layer Specification v2.00.00 for
electrical definitions, specifications, and timing
information. The V_DD_SLVS supply in this data sheet
corresponds to V_DD_TX in the HiSPi Physical Layer
Specification. Similarly, V_DD is equivalent to V_DD_HiSPi
as referenced in the specification. The HiSPi transmitter
electrical specifications are listed at 700 MHz.
Table 16. INPUT VOLTAGE AND CURRENT (HiSPi POWER SUPPLY 0.4 V)
(Measurement Conditions: Max Freq. 700 MHz)
Symbol
Parameter
Min
Typ
Max
Unit
I_DD_SLVS
V_CMD
Supply Current (PWR_HiSPi) (Driving 100 W Load)
HiSPi Common Mode Voltage (Driving 100 W Load)
–
10
15
mA
V_DD_SLVS × V_DD_SLVS/2 V_DD_SLVS ×
V
0.45
0.55
|V_OD|
HiSPi Differential Output Voltage (Driving 100 W Load)
V_DD_SLVS × V_DD_SLVS/2 V_DD_SLVS ×
V
0.36
0.64
DV_CM
|V_OD|
NM
|DV_CM|
|DV_OD|
DV_{CM_ac}
Change in V_CM between Logic 1 and 0
Change in |V_OD| between Logic 1 and 0
V_OD Noise Margin
Difference in V_CM between any Two Channels
Difference in V_OD between any Two Channels
Common-mode AC Voltage (pk) without V_CM Cap
Termination
−
−
25
mV
−
−
25
mV
–
−
30
%
−
−
50
mV
−
−
100
mV
−
−
50
mV
DV_{CM_ac}
V_{OD_ac}
V_{diff_pkpk}
V_eye
R_O
DR_O
Common-mode AC Voltage (pk) with V_CM Cap Termination
Max Overshoot Peak |V_OD|
Max Overshoot V_{diff pk-pk}
Eye Height
Single-ended Output Impedance
Output Impedance Mismatch
−
−
−
1.4 × V_OD
35
−
−
30
mV
−
1.3 × |V_OD|
V
−
2.6 × |V_OD|
V
−
−
50
70
W
−
20
%
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