AR0135CS Datasheet, PDF (19/27 Pages) ON Semiconductor – 1/3‐inch 1.2 Mp CMOS Digital Image Sensor

AR0135CS
V_DIFFmin
Figure 16. Differential Output Voltage for Clock and Data Pairs
V_DIFFmax
0 V (Diff)
Output Signal
is ‘Cp − Cn’ or
‘Dp − Dn’
Table 17. RISE AND FALL TIMES
(Measurement Conditions: HiSPi Power Supply 0.4 V, Max Freq. 700 MHz)
Symbol
Parameter
Min
Typ
Max
Unit
1/UI
Data Rate
280
–
700
Mb/s
TxPRE
Max Setup Time from Transmitter
0.3
–
–
UI (Note 1)
TxPost
RISE
Max Hold Time from Transmitter
Rise Time (20%−80%)
0.3
–
–
UI
–
0.25 UI
–
FALL
Fall Time (20%−80%)
150ps
0.25 UI
–
PLL_DUTY
Clock Duty
45
50
55
%
t_pw
Bitrate Period
1.43
−
3.57
ns (Note 1)
t_eye
Eye Width
0.3
−
−
UI (Notes 1, 2)
t_totaljit
Data Total Jitter (pk pk)@1e−9
−
−
0.2
UI (Notes 1, 2)
t_ckjit
Clock Period Jitter (RMS)
−
−
50
ps (Note 2)
t_cyjit
Clock Cycle-to-Cycle jitter (RMS)
−
−
100
ps (Note 2)
t_chskew
Clock to Data Skew
−0.1
−
0.1
UI (Notes 1, 2)
t_|PHYskew|
PHY-to-PHY Skew
−
−
2.1
UI (Notes 1, 5)
t_DIFFskew
Mean Differential skew
–100
−
100
ps (Note 6)
1. One UI is defined as the normalized mean time between one edge and the following edge of the clock.
2. Taken from 0 V crossing point.
3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates
so the rise and fall times do not exceed the maximum 0.3 UI.
4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges.
5. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges.
6. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two
complementary edges at mean V_CM point.
www.onsemi.com
19