COP888EB Datasheet, PDF (8/75 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 8k Memory, CAN Interface, 8-Bit A/D, and USART

DC Electrical Characteristics COP68xEB (Continued)
Note 11: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at V_CC or GND, and outputs open.
Note 12: The HALT mode will stop CKI from oscillating in the Crystal configurations. Halt test conditions: All inputs tied to V_CC; Port C, G, E, F, L, M and N I/Os con-
figured as outputs and programmed low; D outputs programmed high. Parameter refers to HALT mode entered via setting bit 7 of the Port G data register. Part will
pull up CKI during HALT in crystal clock mode. Both CAN main comparator and the CAN Wakeup comparator need to be disabled.
Note 13: HALT and IDLE current specifications assume CAN block comparators are disabled.
Note 14: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than V_CC and the pins will have isnk current
to V_CC when biased at voltages greater than V_CC (the pins do not have source current when biased at a voltage below V_CC). The effective resistance to V_CC is 750Ω
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 15: Condition and parameter valid only for part in HALT mode.
Note 16: Parameter characterized but not tested.
AC Electrical Characteristics COP68xEB and COP88xEB
−55˚C ≤ T_A ≤ +125˚C
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (t_c)
Crystal/Resonator
Inputs
V_CC ≥ 4.5V
1.0
DC
µs
t_SETUP
t_HOLD
Output Propagation Delay (t_PD1, t_PD0) (Note 19)
SK, SO
All others
MICROWIRE
V_CC ≥ 4.5V
200
V_CC ≥ 4.5V
60
C_L = 100 pF, R_L = 2.2 kΩ
V_CC ≥ 4.5V
V_CC ≥ 4.5V
ns
ns
0.7
µs
1
µs
Setup Time (t_UWS) (Note 20)
Hold Time (t_UWH) (Note 20)
Output Pop Delay (t_UPD)
Input Pulse Width
20
ns
56
ns
220
ns
Interrupt High Time
Interrupt Low Time
Timer 1, 2 High Time
Timer 1, 2 Low Time
Reset Pulse Width (Note 20)
1
t_c
1
t_c
1
t_c
1
t_c
1.0
µs
t_c = Instruction Cycle Time
Note 17: The maximum bus speed achievable with the CAN interface is a function of crystal frequency, message length and software overhead. The device can sup-
port a bus speed of up to 1 Mbit/S with a 10 MHz oscillator and 2 byte messages. The 1M bus speed refers to the rate at which protocol and data bits are transferred
on the bus. Longer messages require slower bus speeds due to the time required for software intervention between data bytes. The device will support a maximum
of 125k bits/s with eight byte messages and a 10 MHz oscillator.
Note 18: For device testing purpose of all AC parameters, V_OH will be tested at 0.5*V_CC.
Note 19: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 20: Parameter not tested.
On-Chip Voltage Reference
−55˚C ≤ T_A ≤ +125˚C
Parameter
Conditions
Min
Reference Voltage
V_REF
Reference Supply
Current, I_DD
I_OUT < 80 µA,
V_CC = 5V
I_OUT = 0A, (No Load)
V_CC = 5V (Note 21)
0.5V_CC −0.12
Note 21: Reference supply I_DD is supplied for information purposes only, it is not tested.
Max
0.5V_CC +0.12
120
Units
V
µA
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