COP888EB Datasheet, PDF (53/75 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 8k Memory, CAN Interface, 8-Bit A/D, and USART

SPI Status Register (Continued)
SPI SYNCHRONIZATION
After the SPI is enabled (SPIEN = 1), the SPI internal re-
ceive and transmit shift clock is kept disabled until SS be-
comes inactive. This includes SS being active at the time
SPIEN is set, i.e., no receive/transmit is possible until SS
becomes inactive after enabling the SPI.
HALT/IDLE MODE
If the device enters the HALT/IDLE mode, both RX and TX
FIFOs get reset (Flushed). If the device is exiting HALT/
IDLE mode, and SPI synchronization takes place as de-
scribed above. SPIRXD and SPITXD have the same state
as after Reset, SPISTAT bits after HALT/IDLE mode are:
SRORN: unchanged
SRBNE: 0
STBF:
0
STBE:
1
STFL:
1
SESSDET: x (depending on SS and MOSI line)
TRANSMISSION START IN MASTER MODE
The transmission of data in the Master mode is started if
the user controlled SS signal is switched active. No SCK
will be generated in Master mode and thus no data is
transmitted if the SS signal is kept high, i.e., SS must be
switched low to generate SCK. Resetting the SS signal in
the Master mode will immediately stop the transmission
and flush the transmit FIFO. Thus, the user must only re-
set the SS if:
1. TBE is set or
2. SCK is high (SCE = 0) or low (SCE = 1)
TX AND RX FIFO
If the SPI is disabled (SPIEN = 0), all SPI FIFO related
pointers are reset and kept at zero until the SPI is enabled
again. Also, the Read/Write operation to both SPITXD and
SPIRXD will not cause the pointers to change, if SPIEN is
set, Read operations from the RXFIFO and Write opera-
tion to TXFIFO will increment the respective Read/Write
pointers.
SPIRXD SPI Receive Data Register
SPIRXD is at address location “009A”. It is a read/write
register.
This register holds the receive data at the current SRRP
location: a COP read operation from this register to the ac-
cumulator will read the RX FIFO at the SRRP location and
increment SRRP afterwards. A write to this register (by the
controllers SW) will write to the RX FIFO at the current
SRRP location. The SRRP is not changed.
Note: During breakpoint the SRRP is not incremented.
A write to this register from the SPI interface side will write to
the current SRWP location and increment SRWP afterwards.
SPITXD SPI Transmit Data Register
SPITXD is at address location “009B”. It is a read/write reg-
ister.
This register holds the transmit data at the current STWP lo-
cation: a write from the controller to this register will write to
the STWP location and increment the STWP afterwards. A
read from the controller to this register will read the TX FIFO
at the current STWP location. The pointer is not changed.
Writing data into this register will start a transmission of data
in the master mode.
Note: No read modify write instructions should be used on this register.
Reading this register from the SPI side will read the byte at
the current STRP location and afterwards increment STRP.
SPI RX FIFO
The SPI RX FIFO is a 12 byte first in first out buffer. SPI RX
FIFO data are read from the controller by reading the
SPIRXD register. A pointer (SRRP) controls the controller
read location. Data is written to this register by the SPI inter-
face. The write location is controlled by the SRWP. SRWP is
incremented after data is stored to the FIFO SRWP is never
decremented SRWP has a roll-over 10 → 11 → 0 → 1 →
2 → etc. It is a circularly linked list.
SRRP is incremented after data is read from the FIFO SRRP
is never decremented SRRP has a roll-over 10 → 11 → 0 →
1 → 2 → etc. It is a circularly linked list.
Both pointers are cleared at reset.
The following bits indicate the status of the RX FIFO:
SRBNE = (SRWP != SRRP) and !SRORN .SRORN is set at
(SRWP = SRRP) and after a write from the SPI side, reset at
write to SPISTAT.
Special conditions: if .SRORN is set, no writes to the RX
FIFO are allowed from the SPI side. SRWP is frozen. Reset-
ting. SRORN (after it was set) clears both SRWP and SRRP.
To prevent erroneous clearing of the Receive FIFO when en-
tering HALT/IDLE mode, the user needs to enable the MIWU
or port M3 (SS) by setting bit 3 in MWKEN register.
SPI TX FIFO
The SPI TX FIFO is a 12 byte first in first out buffer. Data is
written to the FIFO by the controller executing a write instruc-
tion to the SPITXD register. A pointer (STWP) controls the
controller write location. Data is read from this register by the
SPI interface. The read location is controlled by the STRP.
STRP is incremented after data is read from the FIFO STRP
is never decremented STRP has a roll-over 10 → 11 → 0 →
1 → 2 → etc. It is a circularly linked list.
STWP is incremented after data is written to the FIFO STWP
is never decremented STWP has a roll-over 10 → 11 → 0 →
1 → 2 → etc. It is a circularly linked list.
Both pointers are cleared at reset.
The following bits indicate the status of the TX FIFO: STBF
= set at (STRP = STWP) after a write from the controller re-
set at ((STRP != STWP) I STBE) after a read from the SPI
STBE = (STRP = STWP) after a read from the SPI.
Special conditions: If the SS signal becomes high before
data the last bit of the last byte in the TX FIFO is transmitted
both STRP and STWP will be set to 0. The STFL bit will be
set. (STBE will be set as well.)
Note: The SRRP, SRWP, STRP and STWP registers are not available to the
user. Their operation description is included for clarity and to enhance
the user’s understanding.
A/D Converter
The device contains an 8-channel, multiplexed input, suc-
cessive approximation, Analog-to Digital converter. The de-
vice’s V_CC and GND pins are used for voltage reference.
53
www.national.com