COP888EB Datasheet, PDF (20/75 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 8k Memory, CAN Interface, 8-Bit A/D, and USART

Multi-Input Wakeup (Continued)
FIGURE 12. Port M Multi-Input Wake-up Logic
DS012837-13
This same procedure should be used following reset, since
the Port L inputs are left floating as a result of reset. The oc-
currence of the selected trigger condition for Multi-Input
Wakeup is latched to a pending register called WKPND. The
respective bits of the WKPND register will be set on the oc-
currence of the selected trigger edge on the corresponding
Port L and Port M pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected wakeup conditions,
the device will not enter the HALT mode if any wakeup bit is
both enabled and pending. Consequently, the user has the
responsibility of clearing the pending flags before attempting
to enter the HALT mode.
The WKEN, WKPND and WKEDG are all read/write regis-
ters, and are cleared at reset.
PORTS L AND PORT M INTERRUPTS
Ports L and M provides the user with additional fifteen fully
selectable, edge sensitive interrupts which are all vectored
into the same service subroutine.
The interrupt from Ports L and M shares logic with the wake
up circuitry. The register WKEN allows interrupts from Port L
to be individually enabled or disabled. The registers LWKEN
and MWKEN specifies the trigger condition to be either a
positive or a negative edge. Finally, the registers LWKEN
and MWKEN latches in the pending trigger conditions.
The GIE (global interrupt enable) bit enables the interrupt
function. A control flag, LPEN, functions as a global interrupt
enable for Port L interrupts. Setting the LPEN flag will enable
interrupts and vice versa. A separate global pending flag is
not needed since the registers LWKEN and MWKEN are ad-
equate.
Since Ports L and M are also used for waking the device out
of the HALT or IDLE modes, the user can elect to exit the
HALT or IDLE modes either with or without the interrupt en-
abled. If he elects to disable the interrupt, then the device will
restart execution from the instruction immediately following
the instruction that placed the microcontroller in the HALT or
IDLE modes. In the other case, the device will first execute
the interrupt service routine and then revert to normal opera-
tion.
The Wakeup signal will not start the chip running immedi-
ately since crystal oscillators or ceramic resonators have a fi-
nite start up time. The IDLE Timer (T0) generates a fixed de-
lay to ensure that the oscillator has indeed stabilized before
allowing the device to execute instructions. In this case,
upon detecting a valid Wakeup signal, only the oscillator cir-
cuitry and the IDLE Timer T0 are enabled. The IDLE Timer is
loaded with a value of 256 and is clocked from the t_c instruc-
tion cycle clock. The t_c clock is derived by dividing down the
oscillator clock by a factor of 10. A Schmitt trigger following
the CKI on-chip inverter ensures that the IDLE timer is
clocked only when the oscillator has a sufficiently large am-
plitude to meet the Schmitt trigger specifications. This
Schmitt trigger is not part of the oscillator closed loop. The
start-up time-out from the IDLE timer enables the clock sig-
nals to be routed to the rest of the chip.
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