COP888EB Datasheet, PDF (25/75 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 8k Memory, CAN Interface, 8-Bit A/D, and USART

Functional Block Description of
the CAN Interface (Continued)
REGISTER DATA LENGTH CODE AND IDENTIFIERLOW
REGISTER (RIDL)(Address X’00A6)
RID3 RID2 RID1 RID0 RDLC3 RDLC2 RDLC1 RDLC0
Bit 7
Bit 0
This register is read only.
RID3..RID0 Receive Identifier bits (lower four bits)
The RID3..RID0 bits are the lower four bits of the eleven bit
long Receive Identifier. Any received message that matches
the upper 7 bits of the Receive Identifier (RID10..RID4) is ac-
cepted if the Receive Identifier Acceptance Filter (RIAF) bit is
set to zero.
RDLC3..RDLC0 Receive Data Length Code bits
The RDLC3..RDLC0 bits determine the number of data
bytes within a received frame.
RECEIVE IDENTIFIER HIGH (RID)(Address X’00A7)
Reserved RID10 RID9 RID8 RID7 RID6 RID5 RID4
Bit 7
Bit 0
This register is read/write.
Bit 7 is reserved and should be zero.
RID10..RID4 Receive Identifier bits (upper bits)
The RID10...RID4 bits are the upper 7 bits of the eleven bit
long Receive Identifier. If the Receive Identifier Acceptance
Filter (RIAF) bit (see CBUS register) is set to zero, bits 4 to
10 of the received identifier are compared with the mask bits
of RID4..RID10. If the corresponding bits match, the mes-
sage is accepted. If the RIAF bit is set to a one, the filter
function is disabled and all messages, independent of iden-
tifier, will be accepted.
CAN PRESCALER REGISTER (CSCAL)(Address
X’00A8)
CKS7 CKS6 CKS5 CKS4 CKS3 CKS2 CKS1 CKS0
Bit 7
Bit 0
This register is read/write.
CKS7..0 Prescaler divider select.
The resulting clock value is the CAN Prescaler clock.
CAN BUS TIMING REGISTER (CTIM) (Address X’00A9)
PPS2 PPS1 PPS0 PS2 PS1 PS0 Reserved Reserved
Bit 7
Bit 0
This register is read/write.
PPS2..PPS0 Propagation Segment, bits 2..0
The PPS2..PPS0 bits determine the length of the propaga-
tion delay in Prescaler clock cycles (PSC) per bit time. (For
a more detailed discussion of propagation delay and phase
segments, see SYNCHRONIZATION.)
PS2..PS0 Phase Segment 1, bits 2..0
The PS2..PS0 bits fix the number of Prescaler clock cycles
per bit time for phase segment 1 and phase segment 2. The
PS2..PS0 bits also set the synchronization Jump Width to a
value equal to the lesser of: 4 PSC, or the length of PS1/2
(Min: 4 l length of PS1/2).
Bits 1 and 0 are reserved and should be zero.
TABLE 5. Synchronization Jump Width
Length of Synchronization
PS2 PS1 PS0
Phase
Jump Width
Segment ¹â„2
0
0
0
1 t_can
1 t_can
0
0
1
2 t_can
2 t_can
0
1
0
3 t_can
3 t_can
0
1
1
4 t_can
4 t_can
1
0
0
5 t_can
4 t_can
1
0
1
6 t_can
4 t_can
1
1
0
7 t_can
4 t_can
1
1
1
8 t_can
4 t_can
LENGTH OF TIME SEGMENTS (See Figure 28)
• The Synchronization Segment is 1 CAN Prescaler clock
(PSC)
• The Propagation Segment can be programmed (PPS) to
be 1,2...,8 PSC in length.
• Phase Segment 1 and Phase Segment 2 are program-
mable (PS) to be 1,2,..,8 PSC long.
Note: (BTL settings at high speed; PSC = 0) Due to the on-chip delay from
the rx-pins through the receive comparator (worst case assumption: 3
clocks delay * 2 (devices on the bus) + 1 tx delay) the user needs to set
the sample point to (2*3 + 1) i.e., 7 CKI clocks to ensure correct com-
munication on the bus under all circumstances. With prescaler settings
of 0 this is a given (i.e., no caution has to be applied).
Example: for 1 Mbit CTIM = b’10000100 (PSS = 5; PS1 = 2). Example
for 500 kbit CTIM = b’01011100 (PPS = 3; PS1 = 8). − all at 10 MHz
CKI and CSCAL = 0.
CAN BUS CONTROL REGISTER (CBUS) (00AA)
Re- RIAF TxEN1 TxEN0 RxREF1 RxREF0 Re- FMOD
served
served
Bit 7
Bit 0
Reserved These bits are reserved and should be zero.
RIAF
Receive identifier acceptance filter bit
If the RIAF bit is set to zero, bits 4 to 10 of the received iden-
tifier are compared with the mask bits of RID4..RID10 and if
the corresponding bits match, the message is accepted. If
the RIAF bit is set to a one, the filter function is disabled and
all messages independent of the identifier will be accepted.
TxEN0, TxEN1 TxD Output Driver Enable
TABLE 6. Output Drivers
TxEN1
TxEN0
Output
0
0
Tx0, Tx1 TRI-STATE, CAN
input comparator disabled
0
1
Tx0 enabled
1
0
Tx1 enabled
1
1
Tx0 and Tx1 enabled
Bus synchronization of the device is done in the following
way:
If the output was disabled (TxEN1, TxEN0 = “0”) and either
TxEN1 or TxEN0, or both are set to 1, the device will not start
transmission or reception of a frame until eleven consecutive
“recessive” bits have been received. Resetting the TxEN1
and TxEN0 bits will disable the output drivers and the CAN
input comparator. All other CAN related registers and flags
will be unaffected. It is recommended that the user reset the
TxEN1 and TxEN0 bits before switching the device into the
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