COP888EB Datasheet, PDF (47/75 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 8k Memory, CAN Interface, 8-Bit A/D, and USART

Serial Peripheral Interface
FIGURE 36. SPI Transmission Example
DS012837-38
The Serial Peripheral Interface (SPI) is used in master-slave
bus systems. It is a synchronous bidirectional serial commu-
nication interface with two data lines MISO and MOSI (Mas-
ter In Slave Out, Master Out Slave In). A serial clock and a
slave select (SS) signal are always generated by the SPI
Master. The interface receives/transmits protocol frames
with up to 12 bytes length within a frame, where a frame is
defined as the time between a falling edge and a rising edge
of SS.
THEORY OF OPERATION
Figure 38 shows a block diagram illustrating the basic opera-
tion of the SPI circuit. In the SPI interface, data is
transmitted/received in packets of 8 bits length which are
shifted into/out of a shift register with the active edge of the
shift clock SCK. Two 12 byte FIFOs, which serve as a re-
ceive and a transmit buffer, allow a maximum message
length of 12 x 8 bits in both transmit and receive direction
without CPU intervention. With CPU intervention, many
more bytes can be received. Two registers, the SPI Control
Register (SPICNTL) and the SPI Status Register (SPISTAT),
are used to control the SPI interface via the internal COP
bus. Several different operation modes, such as master or
slave operation, are possible.
An SS-Expander allows the generation of up to 8 signals on
the N-port, which can be used as additional SS-signals
(ESS[7:0]) or as host programmable general purpose sig-
nals. The SS-Expander is programmed with the content of
the first MOSI-byte (i.e., the content of the 1st byte [7:0] ap-
pears at ESS[7:0]) (N-port[7:0]), respectively), if the ESS
programming mode is selected. The ESS programming
mode is selected by the condition MOSI = L at the falling
edge of SS.
Use of the ESS expander requires the setup of four condi-
tions by the user.
1. Set the SESSEN bit of SPICNTL.
2. Set PORTNX to select which bits are used for SS expan-
sion.
3. Configure the PORTNC register to enable the desired
SS expansion bits as outputs.
4. Have an ESS condition (MOSI = low at the falling edge
of SS).
Loop Back Mode
Setting the SLOOP bit enables the Loop Back mode, which
can be used for test purposes. If the Loop Back mode is se-
lected, TX FIFO data are communicated to the RX FIFO via
the SPI Register. In the slave mode, MISO output is inter-
nally connected to the MOSI input. In the master mode, the
MOSI output is internally connected to the MISO input.
FIGURE 37. Loop Back Mode Block Diagram
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