COP888EB Datasheet, PDF (13/75 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 8k Memory, CAN Interface, 8-Bit A/D, and USART

Functional Description (Continued)
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (t_c) cycle time.
There are five CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM ad-
dress 02F with reset.
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
Program memory for the device consists of 8 kbytes of ROM.
These bytes may hold program instructions or constant data
(data tables for the LAID instruction, jump vectors for the JID
instruction and interrupt vectors for the VIS instruction). The
program memory is addressed by the 15-bit program
counter (PC). All interrupts in the device vector to program
memory location 0FF Hex.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X and SP pointers.
The device has 192 bytes of RAM. Sixteen bytes of RAM are
mapped as “registers” at addresses 0F0 to 0FF Hex. These
registers can be loaded immediately, and also decremented
and tested with the DRSZ (decrement register and skip if
zero) instruction. The memory pointer registers X, SP, and B
are memory mapped into this space at address locations
0FC to 0FE Hex respectively, with the other registers (other
than reserved register 0FF) being available for general us-
age.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore I/O bits and register bits can be
directly and individually set, reset and tested. The accumula-
tor (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
RESET
The RESET input when pulled low initializes the microcon-
troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for Ports L and G, are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Port D is ini-
tialized high with RESET. The PC, CNTRL, and INCTRL
control registers are cleared. The Multi-Input Wakeup regis-
ters WKEN, WKEDG, and WKPND are cleared. The Stack
Pointer, SP, is initialized to 06F Hex.
The following initializations occur with RESET:
SPI:
SPICNTRL: Cleared
SPISTAT: Cleared
STBE Bit: Set
T1CNTRL & T2CNTRL: Cleared
ITMR: Cleared and IDLE timer period is reset to 4k Instr.
CLK
ENAD: Cleared
ADDSLT: Random
SIOR: Unaffected after RESET with power already ap-
plied.
Random after RESET at power on.
Port L: TRI-STATE
Port G: TRI-STATE
Port D: HIGH
PC: CLEARED
PSW, CNTRL and ICNTRL registers: CLEARED
Accumulator and Timer 1:
RANDOM after RESET with power already applied
RANDOM after RESET at power-on
SP (Stack Pointer): Loaded with 6F Hex
B and X Pointers:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-up
RAM:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-up
CAN:
The CAN Interface comes out of external reset in the
“error-active” state and waits until the user’s soft-
ware sets either one or both of the TXEN0, TXEN1
bits to “1”. After that, the device will not start trans-
mission or reception of a frame util eleven consecu-
tive “recessive” (undriven) bits have been received.
This is done to ensure that the output drivers are not
enamble during an active message on the bus.
CSCAL, CTIM, TCNTL, TEC, REC: CLEARED
RTSTAT: CLEARED with the exception of the TBE bit which
is set to 1
RID, RIDL, TID, TDLC: RANDOM
WATCHDOG:
The device comes out of reset with both the
WATCHDOG logic and the Clock Monitor
detector armed, with the WATCHDOG ser-
vice window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor
circuits are inhibited during reset. The
WATCHDOG service window bits being ini-
tialized high default to the maximum
WATCHDOG service window of 64k t_c clock
cycles. The Clock Monitor bit being initial-
ized high will cause a Clock Monitor bit be-
ing initialized high will cause a Clock Moni-
tor error following reset if the clock has not
reached the minimum specified frequency
at the termination of reset. A Clock Monitor
error will cause an active low error output on
pin G1. This error output will continue until
16 t_c–32 t_c clock cycles following the clock
frequency reaching the minimum specified
value, at which time the G1 output will enter
the TRI-STATE mode.
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