COP888EB Datasheet, PDF (21/75 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 8k Memory, CAN Interface, 8-Bit A/D, and USART

Multi-Input Wakeup (Continued)
FIGURE 13. Port L Multi-Input Wake-Up Logic
DS012837-14
PORT M INTERRUPTS
Port M provides the user with seven fully selectable, edge
sensitive interrupts which are all vectored into the same ser-
vice subroutine.
The interrupt from Port M shares logic with the wake up cir-
cuitry. The MWKEN register allows interrupts from Port M to
be individually enabled or disabled. The MWKEDG register
specifies the trigger condition to be either a positive or a
negative edge. The MWKPND register latches in the pend-
ing trigger conditions.
The LPEN control flag in the ICNTRL register functions as a
global interrupt enable for Port M interrupts. Setting the
LPEN flag enables interrupts. Note that the GIE bit in the
PSW register must also be set to enable these Port L inter-
rupts. A global pending flag is not needed since each pin has
a corresponding pending flag in the MWKPND register.
Since Port M is also used for exiting the device from the
HALT or IDLE mode, the user can elect to exit the HALT or
IDLE mode either with or without the interrupt enabled. If the
user elects to disable the interrupt, then the device restarts
execution from the point at which it was stopped (first in-
struction cycle of the instruction following the enter HALT or
IDLE mode instruction). In the other case, the device finishes
the instruction which was being executed when the part was
stopped (the NOP(Note 26) instruction following the enter
HALT or IDLE mode instruction), and then branches to the
interrupt service routine. The device then reverts to normal
operation.
Note 26: The user must place two NOPs after an enter HALT or IDLE mode
instruction.
To prevent erroneous clearing of the SPI receive FIFO when
entering HALT/IDLE mode, the user needs to enable the
MIWU on port M3. (SS) by setting bit 3 in the MWKEN reg-
ister.
CAN RECEIVE WAKEUP
The CAN Receive Wakeup source can be enabled or dis-
abled. There is no specific enable bit for the CAN Wakeup
feature. Although the wakeup feature on pins L0..17 and
M0..M7 can be programmed to generate an interrupt (Port L
or Port M interrupt), no interrupt is generated upon a CAN re-
ceive wakeup condition. The CAN block has it’s own, dedi-
cated receiver interrupt upon receive buffer full (see CAN
Section).
CAN Wake-Up:
The CAN interface can be programmed to wake the device
from HALT/IDLE mode. This is done by setting bit 7 in the
Port M wake-up enable register (MWKEN). A transition on
the bus will cause the bit 7 of the Port M wake-up pending
(MWKPND) to be set and thereby waking up the device. The
frame on the CAN bus will be lost. The MWEDG (m port
wake-up edge) register bit 7 can be programmed high or low
(high will wake-up on the first falling edge on Rx0).
Resetting bit 7 in the MWKEN will disable the CAN wake-up.
The following sequence should be executed before entering
HALT/IDLE mode:
RBIT 7, MWKPND ;clear CAN wake-up pending
LD A, CBUS
AND A, #0CF ;resetTxEN0 and TxEN1
X A, CBUS ;disable main receive
;comparator
After the device wake-up, the CBUS bits TxEN0 and/or
TxEN1 need be set to allow synchronization on the bus and
to enable transmission/reception of CAN frames.
CAN Block Description *
This device contains a CAN serial bus interface as described
in the CAN Specification Rev. 2.0 part B.
*Patents Pending.
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