COP888EB Datasheet, PDF(19/75 Page) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 8k Memory, CAN Interface, 8-Bit A/D, and USART

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COP888EB Datasheet, PDF (19/75 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 8k Memory, CAN Interface, 8-Bit A/D, and USART

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Power Save Modes (Continued)

256 and is clocked with the tc instruction cycle clock. The tc

clock is derived by dividing the oscillator clock down by a fac-

tor of 10. The Schmitt trigger following the CKI inverter on

the chip ensures that the IDLE timer is clocked only when the

oscillator has a sufficiently large amplitude to meet the

Schmitt trigger specifications. This Schmitt trigger is not part

of the oscillator closed loop. The start-up time-out from the

IDLE timer enables the clock signals to be routed to the rest

of the chip.

The device has two mask options associated with the HALT

mode. The first mask option enables the HALT mode feature,

while the second mask option disables the HALT mode. With

the HALT mode enable mask option, the device will enter

and exit the HALT mode as described above. With the HALT

disable mask option, the device cannot be placed in the

HALT mode (writing a â1â to the HALT flag will have to effect).

IDLE MODE

The device is placed in the IDLE mode by writing a â1â to the

IDLE flag (G6 data bit). In this mode, all activity, except the

associated on-board oscillator circuitry, ad the IDLE Timer

T0, is stopped. The power supply requirements of the micro-

controller in this mode of operation are typically around 30%

of normal power requirement of the microcontroller.

As with the HALT mode, the device can be returned to nor-

mal operation with a reset, or with a Multi-Input Wakeup from

the Port L or CAN Interface. Alternately, the microcontroller

resumes normal operation from the IDLE mode when the

thirteenth bit (representing 4.096 ms at internal clock fre-

quency of 1 MHz, tc = 1 Âµs) of the IDLE Timer toggles.

This toggle condition of the thirteenth bit of the IDLE Timer

T0 is latched into the T0PND pending flag.

The user has the option of being interrupted with a transition

on the thirteenth bit of the IDLE Timer T0. The interrupt can

be enabled or disabled via the T0EN control bit. Setting the

T0EN flag enables the interrupt and vice versa.

The user can enter the IDLE mode with the Timer T0 inter-

rupt enabled. In this case, when the T0PND bit gets set, the

device will first execute the Timer T0 interrupt service routine

and then return to the instruciton following the âEnter Idle

Modeâ instruction.

Alternatively, the user can enter the IDLE mode with the

IDLE Timer T0 interrupt disabled. In this case, the device will

resume normal operation with the instruction immediately

following the âEnter IDLE Modeâ instruction.

Note: It is necessary to program two NOP instructions following both the set

HALT mode and set IDLE mode instructions. These NOP instructions

are necessary to allow clock resynchronization following the HALT or

IDLE modes.

Multi-Input Wakeup

The Multi-Input Wakeup feature is used to return (wakeup)

the device from either the HALT or IDLE modes. Alternately,

the Multi-Input Wakeup/Interrupt feature may also be used to

generate up to 7 edge selectable external interrupts.

Note: The following description is for both the Port L and the M port. When

the document refers to the registers WKEGD, WKEN or WKPND, the

user will have to put either M (for M port) or L (for port) in front of the

Figures 12, 13 shows the Multi-Input Wakeup logic for the

microcontroller. The Multi-Input Wakeup feature utilizes the L

Port. The user selects which particular Port L bit (or combi-

nation of Port L bits) will cause the device to exit the HALT or

IDLE modes. The selection is done through the Reg: WKEN.

The Reg: WKEN is an 8-bit read/write register, which con-

tains a control bit for every Port L bit. Setting a particular

WKEN bit enables a Wakeup from the associated Port L pin.

The user can select whether the trigger condition on the se-

lected Port L pin is going to be either a positive edge (low to

high transition) or a negative edge (high to low transition).

This selection is made via the Reg: WKEDG, which is an

8-bit control register with a bit assigned to each Port L pin.

Setting the control bit will select the trigger condition to be a

negative edge on that particular Port L pin. Resetting the bit

selects the trigger condition to be a positive edge. Changing

an edge select entails several steps in order to avoid a

pseudo Wakeup condition as a result of the edge change.

First, the associated WKEN bit should be reset, followed by

the edge select change in WKEDG. Next, the associated

WKPND bit should be cleared, followed by the associated

WKEN bit being re-enabled.

An example may serve to clarify this procedure. Suppose we

wish to change the edge select from positive (low going high)

to negative (high going low) for Port L bit 5, where bit 5 has

previously been enabled for an input interrupt. The program

would be as follows:

RBIT 5, WKEN ; Disable MIWU

SBIT 5, WKEDG ; Change edge polarity

RBIT 5, WKPND ; Reset pending flag

SBIT 5, WKEN ; Enable MIWU

If the Port L bits have been used as outputs and then

changed to inputs with Multi-Input Wakeup/Interrupt, a safety

procedure should also be followed to avoid inherited pseudo

wakeup conditions. After the selected Port L bits have been

changed from output to input but before the associated

WKEN bits are enabled, the associated edge select bits in

WKEDG should be set or reset for the desired edge selects,

followed by the assoicated WKPND bits being cleared.

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