COP888EB Datasheet, PDF (52/75 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 8k Memory, CAN Interface, 8-Bit A/D, and USART

SPI Status Register (Continued)
TABLE 14. SPI Status Register (SPISTAT) (0099)
Bit 7
SRORN
0
Bit 6
SRBNE
0
Bit 5
STBF
1
Bit 4
STBE
1
Bit 3
STFL
0
Bit 2
SESSDET
0
Bit 1
x
The SPI Status Register is a read only register.
Bit 0
x
0
B7 SRORN
SPI receiver overrun.
This bit is set on the attempt to overwrite valid data in the RX FIFO by the SPI interface. (The condition to
detect this is: SRWP = SRRP & COP has not read the data at SRRP and attempting to write to the RX FIFO
by the SPI interface.) This bit can generate a receive interrupt if the receive interrupt is enabled (SRIE = 1).
(Notes 28, 29, 30)
B6 SRBNE
SPI Receive buffer not empty
This bit is set with a write to the SPI RX FIFO resulting in SRWP ! = SRRP (caution at rollover!). This bit is
reset with the read of the SPIRXD register resulting in SRWP to be equal to SRRP.
B5 STBF
This bit can generate a receive interrupt if enabled with the RIE bit.
SPI Transmit buffer full
This bit is set after a write operation to the SPITXD register (from the COP side), which results in STRP =
STWP. It gets reset as soon as the STRP gets incremented - by the SPI if reading data out of the TX FIFO.
B4 STBE
SPI transmit buffer empty
This bit is set after the last bit of the a read from the SPITXD register, which results in STRP = STWP. It gets
reset as soon as the STWP gets incremented - by the COP if writing data into the TX FIFO. It is set on reset.
B3 STFL
SPI Transmit buffer flush
This bit indicates that the contents of the transmit buffer got discharged by the SS signal becoming high
before all data in the transmit buffer could be transmitted. This bit gets set if the SS signal gets high and
1.STRP ! = STWP or
2.STRP = STWP and the current byte has not been completely transmitted from the SPI shift register
These conditions will reset STRP and STWP to 0. These are virtual pointers and cannot be viewed. (Note 31)
B2 SESSDET SPI SS Expander detection
This bit indicates the detection of a SS expand condition (MOSI = 0 at the falling edge of SS) immediately
after the N-port has been programmed (8th SCK bit, 8 µs at SCK = 1 MHz).
This bit is reset at the rising edge of SS.
1: SS expand condition detected.
0: normal communication. (Note 32)
B1
Reserved
B0
Reserved
Note 28: At this condition the write operation will not be executed and all data get lost.
Note 29: The SRORN bit stays set until the reset condition.
This bit is reset with a dummy write to the SPISTAT register. (As the register is read only a dummy write does not have any effect on any other bits in this register.)
As a result of the SRORN condition, the SRWP becomes frozen (i.e., does not change until the SRORN bit is reset) and the SPI will not store any new data in the
RX FIFO.
Note 30: With the SRRP being still available, the user can read the data in the RX FIFO before resetting the SRORN bit.
Note 31: STRP = STWP & STBE = 1 will generate an interrupt.
This bit gets reset with a write to the SPITXD register.
Note 32: The SPI master must hold SS = 0 long enough to allow the device to read SESSDET. Otherwise the SESSDET information will get lost.
www.national.com
52