COP888GW Datasheet, PDF (7/44 Pages) National Semiconductor (TI) – 8-Bit Microcontroller with Pulse Train Generators

Pin Descriptions (Continued)
Since G6 is an input only pin and G7 is dedicated CKO clock
output pin the associated bits in the data and configuration
registers for G6 and G7 are used for special purpose func-
tions as outlined below Reading the G6 and G7 data bits
will return zeros
Note that the chip will be placed in the HALT mode by writ-
ing a ‘‘1’’ to bit 7 of the Port G Data Register Similarly the
chip will be placed in the IDLE mode by writing a ‘‘1’’ to bit 6
of the Port G Data Register
Writing a ‘‘1’’ to bit 6 of the Port G Configuration Register
enables the MICROWIRE PLUS to operate with the alter-
nate phase of the SK clock
Config Reg
Data Reg
G7
Not Used
HALT
G6
Alternate SK
IDLE
Port G has the following alternate features
G0 INTR (ExternaI Interrupt Input)
G2 T1B (Timer T1 Capture Input)
G3 T1A (Timer T1 I O)
G4 SO (MICROWIRE Serial Data Output)
G5 SK (MICROWIRE SeriaI Clock)
G6 SI (MICROWIRE Serial Data Input)
Port G has the following dedicated functions
G7 CKO OsciIlator dedicated output
Ports C and F are 8-bit I O ports
Port E is an 8-bit I O port It has the following alternate
features
E0 CT1 (Output for counter1 PuIse Train Generator)
E1 CT2 (Output for counter2 Pulse Train Generator)
E2 CT3 (Output for counter3 PuIse Train Generator)
E3 CT4 (Output for counter4 Pulse Train Generator)
Port I is an eight-bit Hi-Z input port
Port D is an 8-bit output port that is preset high when
RESET goes Iow The user can tie two or more D port out-
puts (except D2) together in order to get a higher drive
Functional Description
The architecture of the device is modified Harvard architec-
ture With the Harvard architecture the control store pro-
gram memory (ROM) is separated from the data store mem-
ory (RAM) Both ROM and RAM have their own separate
addressing space with separate address buses The archi-
tecture though based on Harvard architecture permits
transfer of data from ROM to RAM
CPU REGISTERS
The CPU can do an 8-bit addition subtraction logical or
shift operation in one instruction (t_c) cycle time
There are six CPU registers
A is the 8-bit Aocumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer which can be optionally
post auto incremented or decremented
X is an 8-bit alternate RAM address pointer which can be
optionally post auto incremented or decremented
SP is the 8-bit stack pointer which points to the subroutine
interrupt stack (in RAM) The SP is initialized to RAM ad-
dress 06F with reset
S is the 8-bit Data Segment Address Register used to ex-
tend the Iower haIf of the address range (00 to 7F) into 256
data segments of 128 bytes each
All the CPU registers are memory mapped with the excep-
tion of the AccumuIator (A) and the Program Counter (PC)
PROGRAM MEMORY
The program memory consists of 16384 bytes of ROM
These bytes may hoId program instructions or constant data
(data tables for the LAID instruction jump vectors for the
JID instruction and interrupt vectors for the VIS instruction)
The program memory is addressed by the 15-bit program
counter (PC) All interrupts in the devices Vector to program
memory location OFF Hex
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers the I O registers (Configuration Data
and Pin) the control registers the MICROWIRE PLUS SIO
shift register and the various registers and counters asso-
ciated with the timers (with the exception of the IDLE timer)
Data memory is addressed directly by the instruction or indi-
rectly by the B X SP pointers and S register
The data memory consists of 512 bytes of RAM Sixteen
bytes of RAM are mapped as ‘‘registers’’ at addresses 0F0
to 0FF Hex These registers can be loaded immediately
and also decremented and tested with the DRSZ (decre-
ment register and skip if zero) instruction The memory
pointer registers X SP B and S are memory mapped into
this space at address locations 0FC to 0FF Hex respective-
ly with the other registers being available for general usage
Note RAM contents are undefined upon power-up
Data Memory Segment RAM
Extension
Data memory address 0FF is used as a memory mapped
location for the Data Segment Address Register (S)
The data store memory is either addressed directly by a
single-byte address within the instruction or indirectly rela-
tive to the reference of the B X or SP pointers (each con-
tains a single-byte address) This single-byte address allows
an addressing range of 256 locations from 00 to FF hex
The upper bit of this single-byte address divides the data
store memory into two separate sections as outlined previ-
ously With the exception of the RAM register memory from
address locations 00F0 to 00FF all RAM memory is memo-
ry mapped with the upper bit of the single-byte address be-
ing equal to zero This allows the upper bit of the single-byte
address to determine whether or not the base address
range (from 0000 to 00FF) is extended If this upper bit
equals one (representing address range 0080 to 00FF)
then address extension does not take place Alternatively if
this upper bit equals zero then the data segment extension
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