COP888GW Datasheet, PDF (20/44 Pages) National Semiconductor (TI) – 8-Bit Microcontroller with Pulse Train Generators

Power Save Modes (Continued)
factor of 10 The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE timer is clocked only
when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications This Schmitt trigger
is not part of the oscillator closed loop The startup timeout
from the IDLE timer enables the clock signals to be routed
to the rest of the chip
The devices have two mask options associated with the
HALT mode The first mask option enables the HALT mode
feature while the second mask option disables the HALT
mode With the HALT mode enable mask option the device
will enter and exit the HALT mode as described above With
the HALT disable mask option the device cannot be placed
in the HALT mode (writing a ‘‘1’’ to the HALT flag will have
no effect the HALT flag will remain ‘‘0’’)
IDLE MODE
The device is placed in the IDLE mode by writing a ‘‘1’’ to
the IDLE flag (G6 data bit) In this mode all activities except
the associated on-board oscillator circuitry and the IDLE
Timer T0 are stopped
As with the HALT mode the device can be returned to nor-
mal operation with a reset or with a Multi-Input Wake up
from the L Port Alternately the microcontroller resumes
normal operation from the IDLE mode when the thirteenth
bit (representing 4 096 ms at internal clock frequency of
10 MHz t_c e 1 ms) of the IDLE Timer toggles
This toggle condition of the thirteenth bit of the IDLE Timer
T0 is latched into the T0PND pending flag
The user has the option of being interrupted with a transition
on the thirteenth bit of the IDLE Timer T0 The interrupt can
be enabled or disabled via the T0EN control bit Setting the
T0EN flag enables the interrupt and vice versa
The user can enter the IDLE mode with the Timer T0 inter-
rupt enabled In this case when the T0PND bit gets set the
device will first execute the Timer T0 interrupt service rou-
tine and then return to the instruction following the ‘‘Enter
Idle Mode’’ instruction
Alternatively the user can enter the IDLE mode with the
IDLE Timer T0 interrupt disabled In this case the device
will resume normal operation with the instruction immediate-
ly following the ‘‘Enter IDLE Mode’’ instruction
Note
It is necessary to program two NOP instructions following both the
set HALT mode and set IDLE mode instructions These NOP instruc-
tions are necessary to allow clock resynchronization following the
HALT or IDLE modes
Multi-Input Wakeup
The Multi-Input Wake Up feature is used to return (wake up)
the device from either the HALT or IDLE modes Alternately
Multi-Input Wake Up Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts
Figure 13 shows the Multi-Input Wake Up logic
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FIGURE 13 Multi-Input Wake Up Logic
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