COP888GW Datasheet, PDF (23/44 Pages) National Semiconductor (TI) – 8-Bit Microcontroller with Pulse Train Generators

UART (Continued)
UART CONTROL AND STATUS REGISTERS
The operation of the UART is programmed through three
registers ENU ENUR and ENUI The function of the individ-
ual bits in these registers is as follows
ENU-UART Control and Status Register (Address at 0BA)
PEN
0RW
PSEL1
0RW
XBIT9
PSEL0
0RW
CHL1
0RW
CHL0
0RW
ERR
0R
RBFL
0R
TBMT
IR
Bit 7
Bit 0
ENUR-UART Receive Control and Status Register (Address
at 0BB)
DOE FE PE SPARE RBlT9 ATTN XMTG RCVG
0RD 0RD 0RD 0RW
0R 0RW 0R
0R
Bit 7
Bit 0
ENUI-UART Interrupt and Clock Source Register (Address
at 0BC)
STP2 STP78 ETDX SSEL XRCLK XTCLK ERI ETI
0RW 0RW 0RW 0RW 0RW 0RW 0RW 0RW
Bit 7
Bit 0
Bit is not used
0 Bit is cleared on reset
1 Bit is set to one on reset
R Bit is read-only it cannot be written by software
RW Bit is read write
D Bit is cleared on read when read by software as a
one it is cleared automatically Writing to the bit does
not affect its state
DESCRIPTION OF UART REGISTER BITS
ENU UART CONTROL AND STATUS REGISTER
TBMT This bit is set when the UART transfers a byte of
data from the TBUF register into the TSFT register for trans-
mission It is automatically reset when software writes into
the TBUF register
RBFL This bit is set when the UART has received a com-
plete character and has copied it into the RBUF register It
is automatically reset when software reads the character
from RBUF
ERR This bit is a global UART error flag which gets set if
any or a combination of the errors (DOE FE PE) occur
CHL1 CHL0 These bits select the character frame format
Parity is not included and is generated verified by hardware
CHL1 e 0 CHL0 e 0 The frame contains eight data bits
CHL1 e 0 CHL0 e 1 The frame continues seven data
bits
CHL1 e 1 CHL0 e 0 The frame continues nine data bits
CHL1 e 1 CHL0 e 1 Loopback Mode selected Transmit-
ter output internally looped back to
receiver input Nine bit framing for-
mat is used
XBIT9 PSEL0 Programs the ninth bit for transmission
when the UART is operating with nine data bits per frame
For seven or eight data bits per frame this bit in conjunction
with PSEL1 selects parity
PSEL1 PSEL0 Parity select bits
PSEL1 e 0 PSEL0 e 0 Odd Parity (if Parity enabled)
PSEL1 e 0 PSEL1 e 1 Odd Parity (if Parity enabled)
PSEL1 e 1 PSEL0 e 0 Mark(1) (if Parity enabled)
PSEL1 e 1 PSEL1 e 1 Space(0) (if Parity enabled)
PEN This bit enables disables Parity (7- and 8-bit modes
only)
PEN e 0 Parity disabled
PEN e 1 Parity enabled
ENUR UART RECEIVE CONTROL AND STATUS
REGISTER
RCVG This bit is set high whenever a framing error occurs
and goes low when RDX goes high
XMTG This bit is set to indicate that the UART is transmit-
ting It gets reset at the end of the last frame (end of last
Stop bit)
ATTN ATTENTION Mode is enabled while this bit is set
This bit is cleared automatically on receiving a character
with data bit nine set
RBIT9 Contains the ninth data bit received when the UART
is operating with nine data bits per frame
SPARE Reserved for future use
PE Flags a Parity Error
PE e 0 Indicates no Parity Error has been detected since
the last time the ENUR register was read
PE e 1 Indicates the occurrence of a Parity Error
FE Flags a Framing Error
FE e 0 Indicates no Framing Error has been detected
since the last time the ENUR register was read
FE e 1 Indicates the occurrence of a Framing Error
DOE Flags a Data Overrun Error
DOE e 0 Indicates no Data Overrun Error has been detect-
ed since the last time the ENUR register was
read
DOE e 1 Indicates the occurrence of a Data Overrun Error
ENUI UART INTERRUPT AND CLOCK SOURCE
REGISTER
ETI This bit enables disables interrupt from the transmitter
section
ETI e 0 Interrupt from the transmitter is disabled
ETI e 1 Interrupt from the transmitter is enabled
ERI This bit enables disables interrupt from the receiver
section
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