COP888GW Datasheet, PDF (30/44 Pages) National Semiconductor (TI) – 8-Bit Microcontroller with Pulse Train Generators

Interrupts (Continued)
VIS and the vector table must be located in the same
256-byte block (0y00 to 0yFF) except if VIS is located at the
last address of a block In this case the table must be in the
next block The vector table cannot be inserted in the first
256-byte block (y ⁱ 0)
The vector of the maskable interrupt with the lowest rank is
located at 0yE0 (Hi-Order byte) and 0yE1 (Lo-Order byte)
and so forth in increasing rank number The vector of the
maskable interrupt with the highest rank is located at 0yFA
(Hi-Order byte) and 0yFB (Lo-Order byte)
The Software Trap has the highest rank and its vector is
located at 0yFE and 0yFF
If by accident a VIS gets executed and no interrupt is ac-
tive then the PC (Program Counter) will branch to a vector
located at 0yE0 – 0yE1
Warning
A Default VIS interrupt handler routine must be present As
a minimum this handler should confirm that the GIE bit is
cleared (this indicates that the interrupt sequence has been
taken) take care of any required housekeeping restore
context and return Some sort of Warm Restart procedure
should be implemented These events can occur without
any error on the part of the system designer or programmer
Note
There is always the possibility of an interrupt occurring during an
instruction which is attempting to reset the GIE bit or any other inter-
rupt enable bit If this occurs when a single cycle instruction is being
used to reset the interrupt enable bit the interrupt enable bit will be
reset but an interrupt may still occur This is because interrupt pro-
cessing is started at the same time as the interrupt bit is being reset
To avoid this scenario the user should always use a two- three- or
four-cycle instruction to reset interrupt enable bits
Figure 18 shows the Interrupt block diagram
SOFTWARE TRAP
The Software Trap (ST) is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register This may happen when the
PC is pointing beyond the available ROM address space or
when the stack is over-popped
When an ST occurs the user can re-initialize the stack
pointer and do a recovery procedure (similar to reset but
not necessarily containing all of the same initialization pro-
cedures) before restarting
The occurrence of an ST is latched into the ST pending bit
The GIE bit is not affected and the ST pending bit (not
accessible by the user) is used to inhibit other interrupts
and to direct the program to the ST service routine with the
VIS instruction The RPND instruction is used to clear the
software interrupt pending bit This pending bit is also
cleared on reset
The ST has the highest rank among all interrupts
Nothing (except another ST) can interrupt an ST being
serviced
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FIGURE 18 Interrupt Block Diagram
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