COP888GW Datasheet, PDF (29/44 Pages) National Semiconductor (TI) – 8-Bit Microcontroller with Pulse Train Generators

Interrupts
The devices supports a vectored interrupt scheme It sup-
ports a total of fourteen interrupt sources Table VI lists all
the possible device interrupt sources their arbitration rank-
ings and the memory locations reserved for the interrupt
vector for each source
Two bytes of program memory space are reserved for each
interrupt source All interrupt sources except the software
interrupt are maskable Each of the maskable interrupts
have an Enable bit and one or more Pending bits A maska-
ble interrupt is active it its associated enable and pending
bits are set If GlE e 1 and an interrupt is active then the
processor will be interrupted as soon as it is ready to start
executing an instruction except if the above conditions hap-
pen during the Software Trap service routine This excep-
tion is described in the Software Trap sub-section
The interruption process is accomplished with the INTR in-
struction (opcode 00) which is jammed inside the Instruc-
tion Register and replaces the opcode about to be execut-
ed The following steps are performed for every interrupt
1 The GIE (Global Interrupt Enable) bit is reset
2 The address of the instruction about to be executed is
pushed into the stack
3 The PC (Program Counter) branches to address 00FF
This procedure takes 7 t_c cycles to execute
At this time since GIE e 0 other maskable interrupts are
disabled The user is now free to do whatever context
switching is required by saving the context of the machine in
the stack with PUSH instructions The user would then pro-
gram a VIS (Vector Interrupt Select) instruction in order to
branch to the interrupt service routine of the highest priority
interrupt enabled and pending at the time of the VIS Note
that this is not necessarily the interrupt that caused the
branch to address location 00FF Hex prior to the context
switching
Thus if an interrupt with a higher rank than the one which
caused the interruption becomes active before the decision
of which interrupt to service is made by the VIS then the
interrupt with the higher rank will override any lower ones
and will be acknowledged The lower priority interrupt(s) are
still pending however and will cause another interrupt im-
mediately following the completion of the interrupt service
routine associated with the higher priority interrupt just serv-
iced This lower priority interrupt will occur immediately fol-
lowing the RETI (Return from Interrupt) instruction at the
end of the interrupt service routine just completed
Inside the interrupt service routine the associated pending
bit has to be cleared by software The RETI (Return from
Interrupt) instruction at the end of the interrupt service rou-
tine will set the GIE (Global Interrupt Enable) bit allowing
the processor to be interrupted again if another interrupt is
active and pending
The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the
beginning of the service routine of the one with the highest
rank
The addresses of the different interrupt service routines
called vectors are chosen by the user and stored in ROM in
a table starting at 01E0 (assuming that VIS is located be-
tween 00FF and 01DF) The vectors are 15-bit wide and
therefore occupy 2 ROM locations
TABLE VI Interrupt Vector Table
ARBITRATION
RANKING
(1) Highest
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16) Lowest
SOURCE
DESCRIPTION
Software
Reserved
External
Timer T0
Timer T1
Timer T1
Microwire PIus
Counters
UART
UART
Timer T2
Timer T2
Capture Timer 1 and 2
Unused
Port L Wakeup
Default VIS
G0
Underflow
T1A Underflow
T1B
Busy Low
Receive
Transmit
T2A Underflow
T2B
Reserved
VECTOR
ADDRESS
(Hi-Low Byte)
0yFE – 0yFF
0yFC – 0yFD
0yFA-0yFB
0yF8 – 0yF9
0yF6 – 0yF7
0yF4-0yF5
0yF2 – 0yF3
0yF0 – 0yF1
0yEE – 0yEF
0yEC – 0yED
0yEA – 0yEB
0yE8 – 0yE9
0yE6 – 0yE7
0yE4 – 0yE5
0yE2 – 0yE3
0yE0 – 0yE1
y is a variable which represents the VIS block VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last address of a
block In this case the table must be in the next block
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