COP888GW Datasheet, PDF (4/44 Pages) National Semiconductor (TI) – 8-Bit Microcontroller with Pulse Train Generators

AC Electrical Characteristics COP888GW b40 C ^s T_A ^s a85 C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (t_c)
Crystal Resonator
Ceramic
CKI Clock Duty Cycle (Note 5)
Rise Time (Note 5)
Fall Time (Note 5)
2 5V ^s V_CC ^k 4V
25
V_CC ^t 4V
10
f e Max
40
f e 10 MHz Ext Clock
f e 10 MHz Ext Clock
DC
ms
DC
ms
60
%
5
ms
5
ms
Inputs
t_SETUP
t_HOLD
V_CC ^t 4V
200
2 5V ^s V_CC ^k 4V
500
V_CC ^t 4V
60
2 5V ^s V_CC ^k 4V
150
Output Propagation Delay (Note 8)
t_PD1 t_PD0
SO SK
All Others
R_L e 2 2k C_L e 100 pF
V_CC ^t 4V
2 5V ^s V_CC ^k 4V
V_CC ^t 4V
2 5V ^s V_CC ^k 4V
MICROWIRE^TM Setup Time (t_UWS) (Note 6)
V_CC ^t 4V
20
MICROWIRE Hold Time (t_UWH) (Note 6)
V_CC ^t 4V
56
MICROWIRE Output Propagation Delay (t_UPD)
V_CC ^t 4V
Input Pulse Width (Note 7)
Interrupt Input High Time
1
Interrupt Input Low Time
1
Timer 1 2 Input High Time
1
Timer 1 2 Input Low Time
1
Capture Timer High Time
1
ns
ns
ns
ns
07
ms
18
ms
1
ms
25
ms
ns
ns
220
ns
t_c
t_c
t_c
t_c
CKI
Capture Timer Low Time
1
CKI
Reset Pause Width
1
t_c
Note 1 Maximum rate of voltage change to be defined
Note 2 Supply current is measured after running 2000 cydes with a square wave CKI input CKO open inputs at rails and outputs open
Note 3 The HALT mode will stop CKI from oscillatng Test conditions All inputs tied to V_CC L C E F and G port I O’s configured as outputs and programmed
low and not driving a load D outputs programmed low and not driving a load Parameter refers to HALT mode entered via setting bit 7 of the G Port data register
Part will pull up CKI during HALT in crystal clock mode
Note 4 Pins G6 and RESET are designed with a high voltage input network These pins allow input voltages greater than V_CC and the pins will have sink current to
V_CC when biased at voltages greater than V_CC (the pins do not have source current when biased at a voltage below V_CC ) The effective resistance to V_CC is 750X
(typical) These two pins will not latch up The voltage at the pins must be limited to less than 14 volts WARNING Voltages in excess of 14 volts will cause damage
to the pins This warning excludes ESD transients
Note 5 Condition and parameter valid only for part in HALT mode
Note 6 Parameter characterized but not tested
Note 7 t_c e Instruction Cycle Time
Note 8 The output propagation delay is referenced to the end of the instruction cycle where the output change occurs
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TL DD 12065 – 3
FIGURE 2 MICROWIRE PLUS Timing
4