COP888GW Datasheet, PDF (25/44 Pages) National Semiconductor (TI) – 8-Bit Microcontroller with Pulse Train Generators

UART Operation (Continued)
FIGURE 15 Framing Formats
TL DD 12065 – 17
For any of the above framing formats the last Stop bit can
be programmed to be 7 8th of a bit in length If two Stop
bits are selected and the 7 8th bit is set (selected) the
second Stop bit will be 7 8th of a bit in length
The parity is enabled disabled by PEN bit located in the
ENU register Parity is selected for 7- and 8-bit modes only
If parity is enabled (PEN e 1) the parity selection is then
performed by PSEL0 and PSEL1 bits located in the ENU
register
Note that the XBIT9 PSEL0 bit located in the ENU register
serves two mutually exclusive functions This bit programs
the ninth bit for transmission when the UART is operating
with nine data bits per frame There is no parity selection in
this framing format For other framing formats XBIT9 is not
needed and the bit is PSEL0 used in conjunction with
PSEL1 to select parity
The frame formats for the receiver differ from the transmit-
ter in the number of Stop bits required The receiver only
requires one Stop bit in a frame regardless of the setting of
the Stop bit selection bits in the control register Note that
an implicit assumption is made for full duplex UART opera-
tion that the framing formats are the same for the transmit-
ter and receiver
UART INTERRUPTS
The UART is capable of generating interrupts Interrupts are
generated on Receive Buffer Full and Transmit Buffer Emp-
ty Both interrupts have individual interrupt vectors Two
bytes of program memory space are reserved for each inter-
rupt vector The two vectors are located at addresses 0xEC
to 0xEF Hex in the program memory space The interrupts
can be individually enabled or disabled using Enable Trans-
mit Interrupt (ETl) and Enable Receive Interrupt (ERl) bits in
the ENUI register
The interrupt from the Transmitter is set pending and re-
mains pending as long as both the TBMT and ETl bits are
set To remove this interrupt software must either clear the
ETI bit or write to the TBUF register (thus clearing the TBMT
bit)
The interrupt from the receiver is set pending and remains
pending as long as both the RBFL and ERI bits are set To
remove this interrupt software must either clear the ERl bit
or read from the RBUF register (thus clearing the RBFL bit)
Baud Clock Generation
The clock inputs to the transmitter and receiver sections of
the UART can be individually selected to come either from
an external source at the CKX pin (port L pin L1) or from a
source selected in the PSR and BAUD registers Internally
the basic baud clock is created from the oscillator frequency
through a two-stage divider chain consisting of a 1 – 16 (in-
crements of 0 5) prescaler and an 11-bit binary counter (Fig-
ure 16) The divide factors are specified through two read
write registers shown in Figure 17 Note that the 11-bit Baud
Rate Divisor spills over into the Prescaler Select Register
(PSR) PSR is cleared upon reset
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