COP888GW Datasheet, PDF (1/44 Pages) National Semiconductor (TI) – 8-Bit Microcontroller with Pulse Train Generators

PRELIMINARY
September 1996
COP888GW
8-Bit Microcontroller with Pulse Train Generators
and Capture Modules
General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconduc-
tor’s M²CMOS^TM process technology The COP888GW is a
member of this expandable 8-bit core processor family of
microcontrollers It is a fully static part fabricated using dou-
ble-metal silicon gate microCMOS technology
Features include an 8-bit memory mapped architecture MI-
CROWIRE PLUS serial I O two 16-bit timer counters sup-
porting three modes (Processor Independent PWM genera-
tion External Event counter and Input Capture mode capa-
bilities) four independent 16-bit pulse train generators with
16-bit prescalers two independent 16-bit input capture
modules with 8-bit prescalers multiply and divide functions
full duplex UART and two power savings modes (HALT and
IDLE) both with a multi-sourced wake up interrupt capabili-
ty This multi-sourced interrupt capability may also be used
independent of the HALT or IDLE modes
Each I O pin has software selectable configurations The
devices operate over a voltage range of 2 5V–6V High
throughput is achieved with an efficient regular instruction
set operating at a maximum of 1 ms per instruction rate The
device has low EMI emissions Low radiated emissions are
achieved by gradual turn-on output drivers and internal I_CC
filters on the chip logic and crystal oscillator The device is
available in 68-pin PLCC package
Key Features
Y _{Two 16-bit input capture modules with 8-bit prescalers}
Y _{Four Pulse Train Generators with 16-bit prescalers}
Y _{Full duplex UART}
Y _{Two 16-bit timers each with two 16-bit registers}
supporting
Processor independent PWM mode
External event counter mode
Input capture mode
Y _{Quiet design (low radiated emissions)}
Y _{16 kbytes on-board ROM}
Y _{512 bytes on-board RAM}
Additional Peripheral Features
Y _{Idle Timer}
Y _{Multi-Input Wake-Up (MIWU) with optional interrupts (8)}
Y _{MICROWIRE PLUS}TM _{serial I O}
I O Features
Y _{Memory mapped I O}
Y _{Software selectable I O options (TRI-STATE Output}
Push-Pull Output Weak Pull-Up Input High Impedance
Input)
Y _{Schmitt trigger inputs on port G}
Y _{Package 68-pin PLCC}
CPU Instruction Set Features
Y _{1 ms instruction cycle time}
Y _{Fourteen multi-source vectored interrupts servicing}
External Interrupt with selectable edge
Idle Timer T0
Two Timers (each with 2 interrupts)
MICROWIRE PLUS
Multi-Input Wake-Up
Software Trap
UART (2)
Capture Timers
Counters (one vector for all four counters)
Default VIS (default interrupt)
Y _{Versatile and easy-to-use instruction set}
Y _{8-bit Stack Pointer SP (stack in RAM)}
Y _{Two 8-bit register indirect data memory pointers}
(B and X)
Fully Static CMOS
Y _{Two power saving modes HALT and IDLE}
Y _{Low current drain (typically} k_{1 mA)}
Y _{Single supply operation 2 5V – 5 5V}
Y _{Temperature range} b_{40 C to} a_{85 C}
Development Support
Y _{Emulation and OTP device}
Y _{Real time emulation and full program debug offered by}
MetaLink’s Development System
TRI-STATE is a registered trademark of National Semiconductor Corporation
M2CMOSTM MICROWIRE PLUSTM COPSTM MICROWIRETM and WATCHDOGTM are trademarks of National Semiconductor Corporation
IBM PC PC-AT and PC XT are registered trademarks of International Business Machines Corporation
iceMASTERTM is a trademark of MetaLink Corporation
C1996 National Semiconductor Corporation TL DD12065
RRD-B30M106 Printed in U S A
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