COP820CJ Datasheet, PDF (5/35 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 1k or 2k Memory, Comparator and Brown Out Detector

DC Electrical Characteristics (Continued)
−0˚C ≤ T_A ≤ + 70˚C for COP94x and −40˚C ≤ T_A ≤ +85˚C for all others
Parameter
Conditions
Output Current Levels
D Outputs:
Source
Sink
L4–L7 Output Sink
All Others
V_CC = 4.5V, V_OH = 3.8V
V_CC = 2.5V, V_OH = 1.8V
V_CC = 4.5V, V_OL = 1.0V
V_CC = 2.5V, V_OH = 0.4V
V_CC = 4.5V, V_OL = 2.5V
Source (Weak Pull-up Mode)
Source (Push-pull Mode)
Sink (Push-pull Mode)
TRI-STATE Leakage
V_CC = 4.5V, V_OH = 3.2V
V_CC = 2.5V, V_OH = 1.8V
V_CC = 4.5V, V_OH = 3.8V
V_CC = 2.5V, V_OH = 1.8V
V_CC = 4.5V, V_OL = 0.4V
V_CC = 2.5V, V_OL = 0.4V
Allowable Sink/Source
Current Per Pin
D Outputs
L4–L7 (Sink)
All Others
Maximum Input Current
Room Temperature
without Latchup (Note 5)
RAM Retention Voltage, V_r
500 ns Rise and
Fall Time (Min)
Input Capacitance
Load Capacitance on D2
Min
Typ
Max Units
−0.4
−0.2
10
2
15
−10
−2.5
−0.4
−0.2
1.6
0.7
−2.0
mA
mA
mA
mA
mA
−110
µA
−33
µA
mA
mA
mA
mA
+2.0
µA
15
mA
20
mA
3
mA
±100
mA
2.0
V
7
pF
1000
pF
Note 2: Rate of voltage change must be less than 10 V/mS.
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. HALT test conditions: L, and G0..G5 ports configured as outputs and set
high. The D port set to zero. All inputs tied to V_CC. The comparator and the Brown Out circuits are disabled.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than V_CC and the pins will have sink current
to V_CC when biased at voltages greater than V_CC (the pins do not have source current when biased at a voltage below V_CC). The effective resistance to V_CC is 750Ω
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
5
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