COP820CJ Datasheet, PDF (22/35 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 1k or 2k Memory, Comparator and Brown Out Detector

Multi-Input Wake Up (Continued)
pending flags have to be cleared by the user. Setting the
GIE bit high inside the interrupt subroutine allows nested
interrupts.
The software interrupt does not reset the GIE bit. This
means that the controller can be interrupted by other inter-
rupt sources while servicing the software interrupt.
INTERRUPT PROCESSING
The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice. The Global Interrupt Enable (GIE) bit
is reset to disable further interrupts. The microcontroller
then vectors to the address 00FFH and resumes execu-
tion from that address. This process takes 7 cycles to
complete. At the end of the interrupt subroutine, any of the
following three instructions return the processor back to
the main program: RET, RETSK or RETI. Either one of the
three instructions will pop the stack into the program
counter (PC). The stack pointer is then incremented twice.
The RETI instruction additionally sets the GIE bit to
re-enable further interrupts.
Any of the three instructions can be used to return from a
hardware interrupt subroutine. The RETSK instruction
should be used when returning from a software interrupt
subroutine to avoid entering an infinite loop.
Note: There is always the possibility of an interrupt occurring during an in-
struction which is attempting to reset the GIE bit or any other inter-
rupt enable bit. If this occurs when a single cycle instruction is being
used to reset the interrupt enable bit, the interrupt enable bit will be
reset but an interrupt may still occur. This is because interrupt pro-
cessing is started at the same time as the interrupt bit is being re-
set. To avoid this scenario, the user should always use a two, three,
or four cycle instruction to reset interrupt enable bits.
DETECTION OF ILLEGAL CONDITIONS
The device incorporates a hardware mechanism that allows
it to detect illegal conditions which may occur from coding er-
rors, noise, and “brown out” voltage drop situations. Specifi-
cally, it detects cases of executing out of undefined ROM
area and unbalanced tack situations.
Reading an undefined ROM location returns 00 (hexadeci-
mal) as its contents. The opcode for a software interrupt is
also “00”. Thus a program accessing undefined ROM will
cause a software interrupt.
Reading an undefined RAM location returns an FF (hexa-
decimal). The subroutine stack on the device grows down for
each subroutine call. By initializing the stack pointer to the
top of RAM, the first unbalanced return instruction will cause
the stack pointer to address undefined RAM. As a result the
program will attempt to execute from FFFF (hexadecimal),
which is an undefined ROM location and will trigger a soft-
ware interrupt.
FIGURE 17. Interrupt Block Diagram
DS011208-27
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