COP820CJ Datasheet, PDF (23/35 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 1k or 2k Memory, Comparator and Brown Out Detector

Control Registers
CNTRL1 REGISTER (ADDRESS 00EE)
TC3 TC2 TC1 TRUN MSEL IEDG SL1 SL0
Bit 7
Bit 0
The Timer and MICROWIRE control register contains the fol-
lowing bits:
TC3
Timer T1 Mode Control Bit
TC2
Timer T1 Mode Control Bit
TC1
Timer T1 Mode Control Bit
TRUN
Used to start and stop the timer/counter
(1 = run, 0 = stop)
MSEL
Selects G5 and G4 as MICROWIRE signals
SK and SO respectively
IEDG
External interrupt edge polarity select
SL1 and SL0 Select the MICROWIRE clock divide-by
(00 = 2, 01 = 4, 1x = 8)
PSW REGISTER (ADDRESS 00EF)
HC C TPND ENTI IPND BUSY ENI GIE
Bit 7
Bit 0
The PSW register contains the following select bits:
HC Half-Carry Flip/Flop
C
Carry Flip/Flop
TPND Timer T1 interrupt pending
(timer Underflow or capture edge)
ENTI Timer T1 interrupt enable
IPND External interrupt pending
BUSY MICROWIRE busy shifting flag
ENI External interrupt enable
GIE Global interrupt enable (enables interrupts)
The Half-Carry bit is also effected by all the instructions that
effect the Carry flag. The flag values depend upon the in-
struction. For example, after executing the ADC instruction
the values of the Carry and the Half-Carry flag depend upon
the operands involved. However, instructions like SET C and
RESET C will set and clear both the carry flags. Table 10 lists
the instructions that effect the HC and the C flags.
TABLE 10. Instructions Effecting HC and C Flags
Instr.
ADC
SUBC
SET C
RESET C
RRC
HC Flag
Depends on
Operands
Depends on
Operands
Set
Set
Depends on
Operands
C Flag
Depends on
Operands
Depends on
Operands
Set
Set
Depends on
Operands
CNTRL2 REGISTER (ADDRESS 00CC)
MC3 MC2 MC1 CMPEN CMPRD CMPOE WDUDF unused
R/W R/W R/W R/W
R/O
R/W
R/O
Bit 7
Bit 0
MC3 Modulator/Timer Control Bit
MC2 Modulator/Timer Control Bit
MC1 Modulator/Timer Control Bit
CMPEN Comparator Enable Bit
CMPRD Comparator Read Bit
CMPOE Comparator Output Enable Bit
WDUDF WATCHDOG Timer Underflow Bit (Read Only)
WDREG REGISTER (ADDRESS 00CD)
UNUSED
WDREN
Bit 7
Bit 0
WDREN WATCHDOG Reset Enable Bit (Write Once Only)
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