COP820CJ Datasheet, PDF (28/35 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 1k or 2k Memory, Comparator and Brown Out Detector

Instruction Execution Time
Most instructions are single byte (with immediate addressing
mode instruction taking two bytes).
Most single instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per
Instruction
The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.
Arithmetic Instructions (Bytes/Cycles)
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
[B]
Direct
1/1
3/4
1/1
3/4
1/1
3/4
1/1
3/4
1/1
3/4
1/1
3/4
1/1
3/4
1/1
3/4
1/1
1/3
1/1
3/4
1/1
3/4
1/1
3/4
Immed.
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
Instructions Using A & C
Instructions
CLRA
INCA
DECA
LAID
DCOR
RRCA
SWAPA
SC
RC
IFC
IFNC
Bytes/Cycles
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Transfer of Control Instructions
Instructions
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
Bytes/Cycles
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/7
1/1
Memory Transfer Instructions (Bytes/Cycles)
Register
Register Indirect
Indirect Direct Immed. Auto Incr & Decr
[B] [X]
[B+, B−] [X+, X−]
X A,*
1/1 1/3 2/3
1/2
1/3
LD A,*
1/1 1/3 2/3
2/2
1/2
LD B,Imm
1/1
LD B,Imm
2/3
1/3
(If B < 16)
(If B > 15)
LD
3/3
2/2
Mem,Imm
LD
2/3
Reg,Imm
* = > Memory location addressed by B or X or directly.
The following table shows the instructions assigned to un-
used opcodes. This table is for information only. The opera-
tions performed are subject to change without notice. Do not
use these opcodes.
Unused
Opcode
67
Instruction
NOP
Unused
Opcode
B5
Unused
Opcode
60
61
62
Instruction
NOP
NOP
NOP
Unused
Opcode
A9
AF
B1
Instruction
NOP
LD A, [B]
C → HC
8C
RET
B7
99
NOP
B9
9F
LD [B], #i
BF
A7
X A, [B]
A8
NOP
63
NOP
B4
NOP
Instruction
NOP
X A, [X]
NOP
LD A, [X]
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