COP820CJ Datasheet, PDF (24/35 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 1k or 2k Memory, Comparator and Brown Out Detector

Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Address
Contents
00 to 2F
(820CJ)
On-chip RAM bytes (48 bytes)
00 to 6F
(840CJ)
On-chip RAM bytes (112 bytes)
30 to 7F
(820CJ)
Unused RAM Address Space (Reads as All
Ones)
70 to 7F
(840CJ)
Unused RAM Address Space (Reads as All
Ones)
80 to BF Expansion Space for On-Chip EERAM
(Reads Undefined Data)
C0 to C7 Reserved
C8
MIWU Edge Select Register (Reg:WKEDG)
C9
MIWU Enable Register (Reg:WKEN)
CA
MIWU Pending Register (Reg:WKPND)
CB
Reserved
CC
Control2 Register (CNTRL2)
CD
WATCHDOG Register (WDREG)
CE
WATCHDOG Counter (WDCNT)
CF
Modulator Reload (MODRL)
D0
Port L Data Register
D1
Port L Configuration Register
D2
Port L Input Pins (Read Only)
D3
Reserved for Port L
D4
Port G Data Register
D5
Port G Configuration Register
D6
Port G Input Pins (Read Only)
D7
Port I Input Pins (Read Only)
D8 to DB Reserved for Port C
DC
Port D Data Register
DD to DF Reserved for Port D
E0 to EF On-Chip Functions and Registers
E0 to E7 Reserved for Future Parts
E8
Reserved
E9
MICROWIRE Shift Register
EA
Timer Lower Byte
EB
Timer Upper Byte
EC
Timer1 Autoreload Register Lower Byte
ED
Timer1 Autoreload Register Upper Byte
EE
CNTRL1 Control Register
EF
PSW Register
F0 to FF On-Chip RAM Mapped as Registers
FC
X Register
FD
SP Register
FE
B Register
Reading other unused memory locations will return unde-
fined data.
Addressing Modes
There are ten addressing modes, six for operand addressing
and four for transfer of control.
OPERAND ADDRESSING MODES
REGISTER INDIRECT
This is the “normal” addressing mode for the chip. The oper-
and is the data memory addressed by the B or X pointer.
REGISTER INDIRECT WITH AUTO POST INCREMENT
OR DECREMENT
This addressing mode is used with the LD and X instruc-
tions. The operand is the data memory addressed by the B
or X pointer. This is a register indirect mode that automati-
cally post increments or post decrements the B or X pointer
after executing the instruction.
DIRECT
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
IMMEDIATE
The instruction contains an 8-bit immediate field as the oper-
and.
SHORT IMMEDIATE
This addressing mode issued with the LD B,# instruction,
where the immediate # is less than 16. The instruction con-
tains a 4-bit immediate field as the operand.
INDIRECT
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
TRANSFER OF CONTROL ADDRESSING MODES
RELATIVE
This mode is used for the JP instruction with the instruction
field being added to the program counter to produce the next
instruction address. JP has a range from −31 to +32 to allow
a one byte relative jump (JP + 1 is implemented by a NOP in-
struction). There are no “blocks” or “pages” when using JP
since all 15 bits of the PC are used.
ABSOLUTE
This mode is used with the JMP and JSR instructions with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any loca-
tion in the current 4k program memory segment.
ABSOLUTE LONG
This mode is used with the JMPL and JSRL instructions with
the instruction field of 15 bits replacing the entire 15 bits of
the program counter (PC). This allows jumping to any loca-
tion in the entire 32k program memory space.
INDIRECT
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits of
PC) for accessing a location in the program memory. The
contents of this program memory location serves as a partial
address (lower 8 bits of PC) for the jump to the next instruc-
tion.
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