COP820CJ Datasheet, PDF (20/35 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 1k or 2k Memory, Comparator and Brown Out Detector

Modulator/Timer (Continued)
DS011208-18
FIGURE 14. Mode 2a: 50% Duty Cycle Output
DS011208-19
DS011208-20
FIGURE 15. Mode 2b: Variable Duty Cycle Output
Comparator
The device has one differential comparator. Ports L0–L2 are
used for the comparator. The output of the comparator is
brought out to a pin. Port L has the following assignments:
L0 Comparator output
L1 Comparator negative input
L2 Comparator positive input
THE COMPARATOR STATUS/CONTROL BITS
These bits reside in the CNTRL2 Register (Address 0CC)
CMPEN Enables comparator (“1” = enable)
CMPRD Reads comparator output internally
(CMPEN = 1, CMPOE=X)
CMPOE Enables comparator output to pin L0
(“1”=enable), CMPEN bit must be set to enable
this function. If CMPEN=0, L0 will be 0.
The Comparator Select/Control bits are cleared on RESET
(the comparator is disabled). To save power the program
should also disable the comparator before the device enters
the HALT mode.
The user program must set up L0, L1 and L2 ports correctly
for comparator Inputs/Output: L1 and L2 need to be config-
ured as inputs and L0 as output. See Table 9.
TABLE 9. Comparator DC and AC Characteristics
4V ≤ V_CC ≤ 6V, −40˚C ≤ T_A ≤ + 85˚C (Note 7)
Parameters
Conditions
Input Offset Voltage
Input Common Mode Voltage Range
0.4V < V_IN < V_CC − 1.5V
Voltage Gain
DC Supply Current (when enabled)
Response Time
V_CC = 6.0V
100 mV Overdrive
500 mV Overdrive
1000 mV Overdrive
Note 12: For comparator output current characteristics see L-Port specs.
Min
Type
Max
Units
±10
±25
mV
0.4
V_CC − 1.5
V
300k
V/V
250
µA
60
100
140
ns
80
125
165
ns
135
215
300
ns
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