COP820CJ Datasheet, PDF (13/35 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 1k or 2k Memory, Comparator and Brown Out Detector

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TABLE 2. R/C Oscillator Configuration (Part-To-Part Variation)
R
C
(kΩ)
(pF)
3.3
82
5.6
100
6.8
100
CK1 Freq.
(MHz)
2.2 to 2.7
1.1 to 1.3
0.9 to 1.1
Instr. Cycle
(µs)
3.7 to 4.6
7.4 to 9.0
8.8 to 10.8
Conditions
V_CC = 5V
V_CC = 5V
V_CC = 5V
R/C OSCILLATOR (COP840CJ)
For COP840CJ, selecting the R/C oscillator option makes a
R/C oscillator when connecting a resistor from the CKI pin to
V . The capacitor is on-chip. The G7/CKO pin is available as
a general purpose input G7 and/or Halt control. Adding an
external capacitor will jeopardize the clock frequency toler-
ance and increase EMI emissions. Table 3 shows the clock
frequency for the different resistor values.
TABLE 3. RC Oscillator Configuration (Part-To-Part Variation)
R (kΩ)
2.2
4.7
20.0
CK1 Freq. (MHz)
7.0 ± 15%
4.2 ± 10%
7.1 ± 10%
Temperature
-40˚C to +85˚C
-40˚C to +85˚C
-40˚C to +85˚C
V_CC
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
Note 9: The resistance level is calculated with a total of 5.3 pF capacitance added from the printed circuit board. It is important to take this into account when figuring
the clock frequency.
HALT Mode
The device is a fully static device. The device enters the
HALT mode by writing a one to the G7 bit of the G data reg-
ister. Once in the HALT mode, the internal circuitry does not
receive any clock signal and is therefore frozen in the exact
state it was in when halted. In this mode, the chip will only
draw leakage current (output current and DC current due to
the Brown Out circuit if Brown Out is enabled).
The device supports four different methods of exiting the
HALT mode. The first method is with a low to high transition
on the CKO (G7) pin. This method precludes the use of the
crystal clock configuration (since CKO is a dedicated out-
put). It may be used either with an RC clock configuration or
an external clock configuration. The second method of exit-
ing the HALT mode is with the multi-Input Wakeup feature on
the L port. The third method of exiting the HALT mode is by
pulling the RESET input low. The fourth method is with the
operating voltage going below Brown Out voltage (if Brown
Out is enabled by mask option).
If the two pin crystal/resonator oscillator is being used and
Multi-Input Wakeup or Brown Out causes the device to exit
the HALT mode, the WAKEUP signal does not allow the chip
to start running immediately since crystal oscillators have a
delayed start up time to reach full amplitude and freuqency
stability. The WATCHDOG timer (consisting of an 8-bit pres-
caler followed by an 8-bit counter) is used to generate a fixed
delay of 256tc to ensure that the oscillator has indeed stabi-
lized before allowing instruction execution. In this case, upon
detecting a valid WAKEUP signal only the oscillator circuitry
is enabled. The WATCHDOG Counter and Prescaler are
each loaded with a value of FF Hex. The WATCHDOG pres-
caler is clocked with the t_c instruction cycle. (The t_c clock is
derived by dividing the oscillator clock down by a factor of
10). The Schmitt trigger following the CKI inverter on the chip
ensures that the WATCHDOG timer is clocked only when the
oscillator has a sufficiently large amplitude to meet the
Schmitt trigger specs. This Schmitt trigger is not part of the
oscillator closed loop. The start-up timeout from the WATCH-
DOG timer enables the clock signals to be routed to the rest
of the chip. The delay is not activated when the device
comes out of HALT mode through RESET pin. Also, if the
clock option is either RC or External clock, the delay is not
used, but the WATCHDOG Prescaler/Counter contents are
changed. The Development System will not emulate the
256tc delay.
The RESET pin or Brown Out will cause the device to reset
and start executing from address X’0000. A low to high tran-
sition on the G7 pin (if single pin oscillator is used) or
Multi-Input Wakeup will cause the device to start executing
from the address following the HALT instruction.
When RESET pin is used to exit the device from the HALT
mode and the two pin crystal/resonator (CKI/CKO) clock op-
tion is selected, the contents of the Accumulator and the
Timer T1 are undetermined following the reset. All other in-
formation except the WATCHDOG Prescaler/Counter con-
tents is retained until continuing. If the device comes out of
the HALT mode through Brown Out reset, the contents of
data registers and RAM are unknown following the reset. All
information except the WATCHDOG Prescaler/Counter con-
tents is retained if the device exits the HALT mode through
G7 pin or Multi-Input Wakeup.
G7 is the HALT-restart pin, but it can still be used as an input.
If the device is not halted, G7 can be used as a general pur-
pose input.
If the Brown Out Enable mask option is selected, the Brown
Out circuit remains active during the HALT mode causing ad-
ditional current to be drawn.
Note: To allow clock resynchronization, it is necessary to program two NOP’s
immediately after the device comes out of the HALT mode. The user
must program two NOP’s following the “enter HALT mode” (set G7
data bit) instruction.
MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous bidirectional
communications interface. The MICROWIRE/PLUS capabil-
ity enables the device to interface with any of National Semi-
conductor’s MICROWIRE peripherals (i.e. A/D converters,
display drivers, EEPROMS, etc.) and with other microcon-
trollers which support the MICROWIRE/PLUS interface. It
consists of an 8-bit serial shift register (SIO) with serial data
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