COP820CJ Datasheet, PDF (15/35 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 1k or 2k Memory, Comparator and Brown Out Detector

Reset (Continued)
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by the
Master will be shifted properly. After eight clock pulses the
BUSY flag will be cleared and the sequence may be re-
peated. (See Figure 7).
TABLE 5.
G4
G5
Config. Config.
Bit
Bit
1
1
G4
Fun.
SO
0
1 TRI-STATE
1
0
SO
0
0 TRI-STATE
G5 G6
Fun. Fun.
Operation
Int.
SI MICROWIRE
SK
Master
Int.
SI MICROWIRE
SK
Master
Ext. SI MICROWIRE
SK
Slave
Ext. SI MICROWIRE
SK
Slave
MODE 1. TIMER WITH AUTO-LOAD REGISTER
In this mode of operation, the timer T1 counts down at the in-
struction cycle rate. Upon underflow the value in the register
R1 gets automatically reloaded into the timer which contin-
ues to count down. The timer underflow can be programmed
to interrupt the microcontroller. A bit in the control register
CNTRL enables the TIO (G3) pin to toggle upon timer under-
flows. This allows the generation of square-wave outputs or
pulse width modulated outputs under software control
(Figure 8).
MODE 2. EXTERNAL COUNTER
In this mode, the timer T1 becomes a 16-bit external event
counter. The counter counts down upon an edge on the TIO
pin. Control bits in the register CNTRL program the counter
to decrement either on a positive edge or on a negative
edge. Upon underflow the contents of the register R1 are au-
tomatically copied into the counter. The underflow can also
be programmed to generate an interrupt (Figure 9).
Timer/Counter
The device has a powerful 16-bit timer with an associated
16-bit register enabling it to perform extensive timer func-
tions. The timer T1 and its register R1 are each organized as
two 8-bit read/write registers. Control bits in the register CN-
TRL allow the timer to be started and stopped under soft-
ware control. The timer-register pair can be operated in one
of three possible modes. Table 6 details various timer oper-
ating modes and their requisite control settings.
DS011208-24
FIGURE 8. Timer/Counter Auto
Reload Mode Block Diagram
CNTRL
Bits
765
000
001
010
011
100
101
110
111
TABLE 6. Timer Operating Modes
Operation Mode
External Counter w/Auto-Load Reg.
External Counter w/Auto-Load Reg.
Not Allowed
Not Allowed
Timer w/Auto-Load Reg.
Timer w/Auto-Load Reg./Toggle TIO Out
Timer w/Capture Register
Timer w/Capture Register
T Interrupt
Timer Underflow
Timer Underflow
Not Allowed
Not Allowed
Timer Underflow
Timer Underflow
TIO Pos. Edge
TIO Neg. Edge
Timer
Counts
On
TIO Pos. Edge
TIO Neg. Edge
Not Allowed
Not Allowed
t_c
t_c
t_c
t_c
15
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