LM3753 Datasheet, PDF (4/38 Pages) National Semiconductor (TI) – Scalable 2-Phase Synchronous Buck Controllers with Integrated FET Drivers and Linear Regulator Controller

Pin Number
23
23
24
25
26
27
28
29
30
31
32
Pin Name
TRACK
(LM3753)
SS (LM3754)
FREQ
IAVE
EN
CS2
ILIM
CSM
CS1
PH
BOOT2
DAP
Description
Tracking Input. Connect the TRACK pins of all of the controllers in the system together. Wire the
TRACK pin to the external TRACK control signal. Tracking is always enabled on power-up,
shutdown and brownout.
Soft-Start. Connect the SS pins of all of the controllers in the system together. At the Master
controller, connect a soft-start capacitor between SS and SGND. Only the Master controller
supplies the pull up current to the SS capacitor.
Frequency Adjust. A frequency adjust resistor and decoupling capacitor are connected between
FREQ and SGND to program the switching frequency between 200 kHz to 1 MHz (each phase).
These components must be supplied on the Master and Slaves, even if the system is
synchronized to an external clock.
Current Averaging. Connect a 4.02 kΩ, 1%, resistor between each controller’s IAVE pin and
SGND. In the case where one phase is not used, connect an 8.06 kΩ resistor. Connect a filter
capacitor between IAVE and SGND at each controller,
Enable Input. Used for VIN UVLO function, connect EN to the midpoint of a voltage divider from
VIN to SGND. The EN pins of all controllers must be wired together. For an on/off EN function,
wire the EN pins of all controllers together and control with an open drain output.
Positive current-sense input of Phase 2. Connect to the DCR network or the current-sense
resistor of Phase 2. The negative current-sense input is the CSM pin.
Current Limit Set. Connect a resistor between ILIM and CSM. The resistance between ILIM and
CSM programs the current limit.
Negative current-sense input of the internal current-sense amplifiers. Connect to V_OUT.
Positive current-sense input of Phase 1. Connect to the DCR network or the current-sense
resistor of Phase 1. The negative current-sense input is the CSM pin.
Phase Select Input. Connect this pin to the middle of a resistor divider between VCC and SGND
to program the number of phases in the system.
Bootstrap pin of Phase 2 for the high-side gate drive power supply.
Die Attach Pad. Must be connected to PGND and SGND but cannot be used as the primary
ground connection; do not place any traces or vias other than GND in the outer layer under the
DAP; see AN-1187 application note.
www.national.com
4