LM3753 Datasheet, PDF (23/38 Pages) National Semiconductor (TI) – Scalable 2-Phase Synchronous Buck Controllers with Integrated FET Drivers and Linear Regulator Controller

general rule is to make the damping capacitor at least five
times the value of the ceramic. By sizing the aluminum such
that it is primarily resistive at the switching frequency, the de-
sign is greatly simplified since the ceramic capacitors are
primarily reactive. In this case the approximation for the rms
current in the damping capacitor is:
I_{L_VL} = I_OUT − 0.5 x ΔI_L
I_{L_PK} = I_OUT + 0.5 x ΔI_L
Where C_IN2 is the damping capacitance, R_CIN2 is its series
resistance and C_IN1 is the ceramic capacitance. A 470 μF,
25V, 0.06Ω, 1.19A rms aluminum electrolytic capacitor in a
10 mm x 10.2 mm package is chosen for the damping capac-
itor. Calculated rms current for the aluminum electrolytic is
0.67A.
MOSFETS
Selection of the power MOSFETs is governed by a tradeoff
between cost, size and efficiency.
Losses in the high-side FET can be broken down into con-
duction loss, gate charge loss and switching loss. Conduction
or I²R loss is approximately:
P_{COND_HI} = D x (I_OUT2 x R_{DS(on)_HI} x 1.3)
(High-side FET)
P_{COND_LO} = (1 − D) x (I_OUT2 x R_{DS(on)_LO} x 1.3)
(Low-side FET)
In the above equations the factor 1.3 accounts for the in-
crease in MOSFET R_DS(on) due to self heating. Alternatively,
the 1.3 can be ignored and the R_DS(on) of the MOSFET esti-
mated using the R_DS(on) vs. Temperature curves in the MOS-
FET datasheets.
The gate charge loss results from the current driving the gate
capacitance of the power MOSFETs, and is approximated as:
P_DR = V_IN x (Q_{G_HI} + Q_{G_LO}) x f_SW
Where Q_{G_HI} and Q_{G_LO} are the total gate charge of the high-
side and low-side FETs respectively at the typical 5V driver
voltage. Gate charge loss differs from conduction and switch-
ing losses in that the majority of dissipation occurs in the
LM3753/54 and VDD regulator.
The switching loss occurs during the brief transition period as
the FET turns on and off, during which both current and volt-
age is present in the channel of the FET. This can be approx-
imated as:
Where Q_GD is the high-side FET Miller charge with a V_DS
swing between 0 to V_IN; C_ISS is the input capacitance of the
high-side MOSFET in its off state with V_DS = V_IN. α and β are
fitting coefficient numbers, which are usually between 0.5 to
1, depending on the board level parasitic inductances and re-
verse recovery of the low-side power MOSFET body diode.
Under ideal condition, setting α = β = 0.5 is a good starting
point. Other variables are defined as:
R_{G_ON} = 5 + R_{G_INT} + R_{G_EXT}
R_{G_OFF} = 2 + R_{G_INT} + R_{G_EXT}
Switching loss is calculated for the high-side FET only. 5 and
2 represent the LM3753/54 high-side driver resistance in the
transient region. R_{G_INT} is the gate resistance of the high-side
FET, and R_{G_EXT} is the extra external gate resistance if ap-
plicable. R_{G_EXT} may be used to damp out excessive parasitic
ringing at the switch node.
For this example, the maximum drain-to-source voltage ap-
plied to either MOSFET is 18V. The maximum drive voltage
at the gate of the high-side MOSFET is 5V, and the maximum
drive voltage for the low-side MOSFET is 5V. The selected
MOSFET must be able to withstand 18V plus any ringing from
drain to source, and be able to handle at least 5V plus ringing
from gate to source. If the duty cycle of the converter is small,
then the high-side MOSFET should be selected with a low
gate charge in order to minimize switching loss whereas the
bottom MOSFET should have a low R_DS(on) to minimize con-
duction loss.
For a typical input voltage of 12V and output current of 25A
per phase, the MOSFET selections for the design example
are SIR850DP for the high-side MOSFET and 2 x SIR892DP
for the low-side MOSFET.
A 2.2Ω resistor for the high-side gate drive may be added in
series with the HG output. This helps to control the MOSFET
turn-on and ringing at the switch node. Additionally, 0.5A
Schottky diodes may be placed across the high-side MOS-
FETs. The external Schottky diodes have a much faster re-
covery characteristic than the MOSFET body diode, and help
to minimize switching spikes by clamping the SW pin to VIN.
Another technique to control ringing at the switch node is to
place an RC snubber from SW to PGND directly across the
low-side MOSFET. Typical values at 300 kHz are 1Ω and 680
pF.
To improve efficiency, 3A Schottky diodes may be placed
across the low-side MOSFETs. The external Schottky diodes
have a much lower forward voltage than the MOSFET body
diode, and help to minimize the loss due to the body diode
recovery characteristic.
EN and VIN UVLO
For operation at 6V minimum input, set the EN divider to en-
able the LM3753/54 at approximately 5.5V nominal. Values
of R_UV1 = 1.37 kΩ and R_UV2 = 4.02 kΩ will meet the target
threshold.
CURRENT SENSE
For resistor current sense, a 1 mΩ 1W resistor is used for a
full scale voltage of 25 mV at 25A out.
For DCR sensing, R_S is equal to the inductor resistance of
R_L = 0.32 mΩ plus an estimated trace resistance of 0.2 mΩ..
The full scale voltage is about 13 mV at 25A. For equal time
constants, the relationship of the integrating RC is determined
by:
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