LM3753 Datasheet, PDF (18/38 Pages) National Semiconductor (TI) – Scalable 2-Phase Synchronous Buck Controllers with Integrated FET Drivers and Linear Regulator Controller

tom of the Master feedback divider at SGND. The COMP pin
of each Slave is connected to its corresponding VDIF pin. This
provides sufficient buffering of the master COMP signal for
the internal summing of the current averaging circuit.
OSCILLATOR and SYNCHRONIZATION
A resistor and decoupling capacitor are connected between
FREQ and SGND to program the switching frequency be-
tween 200 kHz to 1 MHz. These components must be sup-
plied on each controller, even if the system is synchronized
to an external clock.
The switching frequency and synchronization are controlled
by the Master. The Master can switch in a free-running mode
or be synchronized to an external clock. To synchronize the
Master apply the external clock to the SYNC pin of the Master,
otherwise ground this pin. The amplitude of the signal on the
SYNC pin must be limited to be between 0V and VCC.
The value of the frequency setting resistor is determined as:
NFET SYNCHRONOUS DRIVERS
The LM3753/54 has two sets of gate drivers designed for
driving N-channel MOSFETs in a synchronous mode. Power
to the high-side driver is supplied through the BOOT pin. For
the high-side gate HG to turn on the high-side FET, the BOOT
voltage must be at least one V_GS greater than VIN. This volt-
age is supplied from a local charge pump which consists of a
Schottky diode and bootstrap capacitor, shown in Figure 6.
For the Schottky, a rating of at least 250 mA and 30V is rec-
ommended. A dual package may be used to supply both
BOOT1 and BOOT2 for each controller.
Both the bootstrap and the low-side FET driver are fed from
VDD. The drive voltage for the top FET driver is about VDD
− 0.5V at light load condition and about VDD at normal to full
load condition.
A 1000 pF ceramic capacitor is used to provide sufficient de-
coupling. If the Master is synchronized set the resistor ac-
cording the nominal applied frequency. If the signal on the
SYNC pin is below 150 kHz the signal will be ignored and the
device will revert to free-running mode. The SYNCOUT signal
from the Master is applied to the first Slave’s SYNC pin. The
SYNCOUT pin of the first Slave is connected to the SYNC pin
of the second Slave, and so on, in a daisy chain configuration.
SYNCOUT of the last Slave (or the Master in a single con-
troller system) is left unconnected.
The configuration of the system, namely the number of con-
trollers and phases is programmed by the voltage on the PH
pin. For each controller connect the midpoint of a resistor di-
vider between VCC and SGND to the PH pin. The division
ratios are given in the Electrical Characteristics table and
nominal resistor values in Table 1. This sets the phase shift
between SYNC and the SYNCOUT pin. Where an even num-
ber of phases (N) are employed, the phase delay from SYNC
to SYNCOUT is 360°/N. The phase difference between the
two phases on the same controller is 180°. For systems with
an odd number of the phases, the HG2 and LG2 gate drivers
on the last Slave are unconnected and the phase arrange-
ment is set according to Table 1
DUTY CYCLE LIMITATION
The minimum controllable on-time is typically 50 ns. This lim-
its the maximum V_IN , V_OUT and f_SW combination.
f_SW < (V_OUT / V_IN) x 20 MHz
The maximum guaranteed duty cycle is 81%. This limits the
minimum V_IN to V_OUT ratio.
(V_OUT / V_IN) x 1.25 < 0.81
The 1.25 term allows margin for efficiency and transient re-
sponse.
THERMAL SHUTDOWN
The internal thermal shutdown circuit causes the PWM con-
trol circuitry to be reset and the NFET drivers to turn off all
external power MOSFETs. The controller remains enabled
and all bias circuitry remains on. After the die temperature
falls below the lower hysteresis point, the controller will
restart.
FIGURE 6. Bootstrap Circuit
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REMOTE SENSE DIFFERENTIAL AMPLIFIER
The differential amplifier connected internally to the SNSP,
SNSM and VDIF pins is a single stage unity gain Instrumen-
tation amplifier. The differential gain is tightly controlled to
within 0.4%.
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FIGURE 7. Differential Amplifier
On the master controller, the differential amplifier is used to
provide Kelvin sensing of the output voltage at the load. This
provides the most accurate sampling for load regulation.
On the slave controllers, the differential amplifier is used to
sense the COMP signal of the master controller with respect
to its signal ground and drive the COMP pin of that slave con-
troller relative to its local signal ground. This allows the master
controller to accurately provide the target duty cycle of the
slave controllers.
The differential amplifier has a low output impedance to allow
it to drive the COMP pins of the Slave controllers. This is nec-
essary because the current sense signal is internally added
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