LM3753 Datasheet, PDF (26/38 Pages) National Semiconductor (TI) – Scalable 2-Phase Synchronous Buck Controllers with Integrated FET Drivers and Linear Regulator Controller

FIGURE 14. Power Stage Gain
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In general, the goal of the compensation circuit is to give high
gain, a bandwidth that is between one-fifth and one-tenth of
the switching frequency, and at least 45° of phase margin.
Control Loop Design Procedure
Once the power stage design is complete, the power stage
components are used to determine the proper frequency
compensation. Knowing the dc modulator gain and assuming
an ideal single-pole system response, the mid-band error am-
plifier gain is set by the target crossover frequency. Based on
the ideal amplifier transfer function, the zero-pair is set to
cancel the complex conjugate pole of the output filter. One
pole is set to cancel the ESR of the output capacitor. The
second pole is set equal to the switching frequency. A cor-
rection factor is used to accommodate the modulator damping
when the output filter pole is within a decade of the target
crossover frequency.
The compensation components will scale from the feedback
divider ratio and selection of the bottom feedback divider re-
sistor. A maximum value for the divider current is typically set
at 1 mA. Using a divider current of 200 μA will allow for a
reasonable range of values. For the bottom feedback resistor
R_FBB = V_REF / 200 μA = 3 kΩ. Choosing a standard 1% value
of 3.01 kΩ, the top feedback resistor is found from:
For V_OUT = 1.2V and V_REF = 0.6V, R_FBT = 3.01 kΩ.
Based on the previously defined power stage values, calcu-
late general terms:
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FIGURE 15. Power Stage Phase
Assuming a pole at the origin, the simplified equation for the
error amplifier transfer function can be written in terms of the
mid-band gain as:
Where:
For the design example D = 0.1, R_i = 0.026Ω, T = 3.33 μs and
K_m = 3.22.
Calculate the output filter pole frequency and the ESR zero
frequency from:
For the output filter pole using C_O = C_O1 + C_O2, ω_P = 68.5 krad/
sec. Since C_O1 >> C_O2, the ESR zero is calculated using
C_O1 and R_C1 as ω_Z = 909 krad/sec.
Choose a target crossover frequency f_C greater than the min-
imum control loop bandwidth from the OUTPUT CAPACI-
TORS section. The optimum value of the crossover frequency
is usually between 5 and 10 times the filter pole frequency.
With f_P = ω_P / (2 x π) = 10.9 kHz, this places f_C between 54.5
kHz and 109 kHz. The upper limit for f_C is typically set at 1/5
of the switching frequency.
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Choosing f_C = 60 kHz for the design example ω_C = 377 krad/
sec. The switching frequency is ω_SW = 1.88 Mrad/sec.
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