LM3753 Datasheet, PDF (15/38 Pages) National Semiconductor (TI) – Scalable 2-Phase Synchronous Buck Controllers with Integrated FET Drivers and Linear Regulator Controller

voltage divider using open-drain logic or a transistor. A cus-
tomary implementation uses an external MOSFET.
30091921
FIGURE 2. Power Connections Using a System 5V Rail
30091923
FIGURE 3. Power Connections for V_IN = 5V
UNDER-VOLTAGE LOCKOUTS and ENABLE
The LM3753/54 controller has internal under-voltage lockout
(UVLO) detection on the VCC and VDD supplies. The under-
voltage lockout on VIN is set using the EN pin threshold.
Connect a voltage divider between VIN and SGND with the
midpoint going to the EN pin. The division ratio and the EN
pin threshold determine the VIN level that enables the con-
troller. This divider should be used in all cases. If the system
does not have a particular VIN under-voltage lockout require-
ment, the level is set to be below the minimum VIN level at
the worst case combination of tolerances and operating con-
ditions.
To guarantee startup at the lowest input voltage, set the di-
vider to the V_EN-TH rising max specification. For a higher
accuracy VIN UVLO operation, the resistor divider minimum
current should be 1 mA or higher. This will reduce the thresh-
old error contribution of the EN pin bias current, which is
guaranteed to be less than 1.7 µA over temperature. The en-
able pin can also be used as a digital on-off. To do this, the
enable signal should be used to pull down the midpoint of the
30091924
FIGURE 4. Input Voltage UVLO with External Enable
While the EN pin has a threshold hysteresis of 140 mV typical,
a small noise-filtering capacitor may be added between the
EN pin and SGND. This is particularly useful when the con-
troller is turning on via the resistor divider by a slowly rising
VIN rail.
STARTUP SEQUENCE
During the initial startup phase the LM3753 and LM3754 be-
have identically. When EN is below its threshold, the internal
regulators are off and the controller is in a low power state.
When EN crosses above its threshold the VCC regulator turns
on. When VCC rises above its under-voltage lockout thresh-
old the VDD regulator turns on. When VDD rises above its
under-voltage lockout threshold the controller is ready to start.
If VDD or VCC is supplied externally and already sitting above
its under-voltage lockout point, then the controller is ready for
startup as soon as EN crosses above its threshold. Anytime
VCC or VDD drops below its UV threshold, switching stops
and the controller goes into a standby state. It will go through
normal startup once the supplies recover.
When the controller is ready to start, it reads the voltage on
the PH pin and determines how many phases are running in
the system. By this means the phase delay from SYNC to
SYNCOUT through the PLL is configured. Following this the
oscillator and PLL turn on and pulses will be observed on
SYNCOUT.
A 2 ms timer is initiated so that all of the PLLs in the system
can synchronize up. As each controller times out, it stops
pulling its FAULT pin low. At the end of this sequence, the
FAULT bus rises and the controllers are ready to switch.
On both the LM3753 and LM3754, the error amplifier uses a
different input stage when TRACK/SS is below VREF. During
normal operation the error amplifier employs a low offset
bipolar input stage. At startup, the input bias current of this
stage is large enough in relation to the soft-start current to
affect the soft-start timing. A MOS input stage is used during
the soft-start or track phase which has a lower input bias cur-
rent but a higher input offset voltage. A 40 mV offset is
introduced when TRACK/SS is less than 70 mV. This offset
forces the error amplifier output to be low during startup. The
offset transitions progressively to zero as TRACK/SS moves
from 0 to 70 mV.
TRACKING (LM3753)
The LM3753 implements a tracking function. The error am-
plifier amplifies the minimum of VREF or TRACK at the FB
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