LM3753 Datasheet, PDF (28/38 Pages) National Semiconductor (TI) – Scalable 2-Phase Synchronous Buck Controllers with Integrated FET Drivers and Linear Regulator Controller

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FIGURE 18. Control Loop Gain
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FIGURE 19. Control Loop Phase
For the small-signal analysis, it is assumed that the control
voltage at the COMP pin is dc. In practice, the output ripple
voltage is amplified by the error amplifier gain at the switching
frequency, which appears at the COMP pin adding to the
control ramp. This tends to reduce the modulator gain, which
may lower the actual control loop crossover frequency. This
effect is greatly reduced as the number of phases is in-
creased.
Efficiency and Thermal
Considerations
The buck regulator steps down the input voltage and has a
duty ratio D of:
Where η is the estimated converter efficiency. The efficiency
is defined as:
The total power dissipated in the power components can be
obtained by adding together the loss as mentioned in the
OUTPUT INDUCTORS, OUTPUT CAPACITORS, INPUT
CAPACITORS and MOSFETS sections.
The highest power dissipating components are the power
MOSFETs. The easiest way to determine the power dissipat-
ed in the MOSFETs is to measure the total conversion loss
(P_IN − P_OUT), then subtract the power loss in the capacitors,
inductors, LM3753/54 and VDD regulator. The resulting pow-
er loss is primarily in the switching MOSFETs. Selecting
MOSFETs with exposed pads will aid the power dissipation
of these devices. Careful attention to R_DS(on) at high temper-
ature should be observed.
If a snubber is used, the power loss can be estimated with an
oscilloscope by observation of the resistor voltage drop at
both the turn-on and turn-off transitions. Assuming that the
RC time constant is << 1 / f_SW:
P = ½ x C x (V_P2 + V_N2) x f_SW
V_P and V_N represent the positive and negative peak voltage
across the snubber resistor, which is ideally equal to V_IN.
LM3753/54 and VDD REGULATOR OPERATING LOSS
These terms accounts for the currents drawn at the VIN and
VDD pins, used for driving the logic circuitry and the power
MOSFETs. For the LM3753/54, the VIN current is equal to the
steady state operating current I_VIN. The VDD current is pri-
marily determined by the MOSFET gate charge current I_GC,
which is defined as:
I_GC = Q_{G_TOTAL} x f_SW
P_D = (V_IN x I_VIN) + (V_DD x I_GC)
Q_{G_TOTAL} is the total gate charge of the MOSFETs connected
to each LM3753/54. P_D represents the total power dissipated
in each LM3753/54. I_VIN is about 15 mA from the Electrical
Characteristics table. The LM3753/54 has an exposed ther-
mal pad to aid power dissipation.
The power dissipated in the VDD regulator is determined by:
P_R = (V_IN − V_DD) x I_{GC_TOTAL}
I_{GC_TOTAL} is the sum of the MOSFET gate charge currents for
all of the controllers.
Layout Considerations
To produce an optimal power solution with a switching con-
verter, as much care must be taken with the layout and design
of the printed circuit board as with the component selection.
The following are several guidelines to aid in creating a good
layout.
KELVIN TRACES for GATE DRIVE and SENSE LINES
The HG and SW pins provide the gate drive and return for the
high-side MOSFETs. These lines should run as parallel pairs
to each MOSFET, being connected as close as possible to
the respective MOSFET gate and source. Likewise the LG
and PGND pins provide the gate drive and return for the low-
side MOSFETs. A good ground plane between the PGND pin
and the low-side MOSFETs source connections is needed to
carry the return current for the low-side gates.
The SNSP and SNSM pins of the Master should be connected
as a parallel pair, running from the output power and ground
sense points. Keep these lines away from the switch node
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