LM3753 Datasheet, PDF (24/38 Pages) National Semiconductor (TI) – Scalable 2-Phase Synchronous Buck Controllers with Integrated FET Drivers and Linear Regulator Controller

Choosing C_DCR = 0.15 μF:
R_DCR = 440 nH / (0.15 μF x 0.52 mΩ) = 5.64 kΩ.
Using a standard value of 5.90 kΩ, the average current
through R_DCR is calculated as 203 μA from:
I_DCR = V_OUT / R_DCR
I_DCR is sufficiently high enough to keep the CS input bias cur-
rent from being a significant error term.
CURRENT LIMIT
For the design example, the desired current limit set point is
chosen as 34.5A peak per phase, which is about 25% above
the full load peak value. Using DCR sense with R_S = 0.52
mΩ:
R_ILIM = 34.5A x 0.52 mΩ / 94 μA = 191Ω
For resistor sense, the relatively low output inductor value
forms a voltage divider with the intrinsic inductance of the
sense resistor. When the MOSFETs switch, this adds a step
to the otherwise triangular current sense voltage. The step
voltage is simply the input voltage times the inductive divider.
With L = 440 nH and L_S = 1 nH, the step voltage is:
V_LS = 12V x 1 nH / 441 nH = 27.2 mV
Using the same method as DCR sense, an RC filter is added
to recover the actual resistive sense voltage. Choosing C = 1
nF the resistor is calculated as:
R = 1 nH / (1 nF x 1 mΩ) = 1 kΩ
The current limit resistor is then calculated as:
R_ILIM = 34.5A x 1 mΩ / 94 μA = 367Ω
The closest standard value of 365Ω 1% is selected for the
design example.
TRACK (LM3753)
For the design example, an external voltage of 3.3V is used
as the controlling voltage. The divider values are set so that
both voltages will rise together, with V_EXT reaching its final
value just before V_OUT. Following the method in the Applica-
tion Information under TRACKING (LM3753) and allowing for
a 120 mV offset between FB and TRACK, standard 1% values
are selected for R_T1 = 10 kΩ and R_T2 = 35.7 kΩ.
SOFT-START (LM3754)
To prevent over-shoot, the soft-start time is set to be longer
than the time it would take to charge the output voltage at the
maximum output current. Following the equations in the Ap-
plication Information under SOFT-START (LM3754):
t_SS(MIN) = (1.2V x 484 μF) / (34.5A − 25A) = 61 μs
Choosing a value of C_SS = 0.1 μF, the soft-start time is:
t_SS = (0.1 μF x 0.6V) / 10 μA = 6 ms
VCC, VDD and BOOT
VCC is used as the supply for the internal control and logic
circuitry. A 4.7 μF ceramic capacitor provides sufficient filter-
ing for VCC.
C_VDD provides power for both the high-side and low-side
MOSGET gate drives, and is sized to meet the total gate drive
current. Allowing for ΔV_VDD = 100 mV of ripple, the minimum
value for C_VDD is found from:
Using Q_{G_HI} = 2 x 10 nC and Q_{G_LO} = 4 x 21 nC per controller
with a 5V gate drive, the minimum value for C_VDD = 1.04 μF.
To use common component values, C_VDD1 and C_VDD2 are also
selected as 4.7 μF ceramic.
A general purpose NPN transistor is sized to meet the re-
quirements for the VDD supply. Based on the gate charge of
104 nC per controller, the required current is found from:
I_GC = Q_{G_TOTAL} x f_SW
At 300 kHz, I_GC = 31.2 mA per controller. For a two controller
system, the minimum HFE for the transistor is determined by:
HFE_MIN = I_{GC_TOTAL} / 5 mA
The power dissipated by the transistor is:
P_R = (V_IN − V_DD) x I_{GC_TOTAL}
The transistor must support 62.4 mA with an HFE of at least
12.5 over the entire operating range. At 18V in the power dis-
sipated is 0.8W. A CJD44H11 in a DPAK case is chosen for
the design example. A 0.047 μF capacitor from base to PGND
will improve the transient performance of the VDD supply.
C_BOOT provides power for the high-side gate drive, and is
sized to meet the required gate drive current. Allowing for
ΔV_BOOT = 100 mV of ripple, the minimum value for C_BOOT is
found from:
Using Q_{G_HI} = 10 nC per phase with a 5V gate drive, the min-
imum value for C_BOOT = 0.1 μF. C_BOOT is selected as 0.22 μF
ceramic per phase for the design example. A 0.5A Schottky
diode is used for D_BOOT at each controller.
PRE-LOAD RESISTOR
For normal operation, a pre-load resistor is generally not re-
quired. During an abnormal fault condition with the output
completely disconnected from the load, the output voltage
may rise. This is primarily due to the high-side driver off-state
bias current, and reverse leakage current of the high-side
Schottky clamp diode.
At room temperature with 12V input, the reverse leakage of
each 0.5A Schottky diode is about 15 μA. With the EN pin high
and the FAULT pin low, the bias current in each high-side
driver is about 105 μA. Allowing for a 2 to 1 variation, the
maximum value of resistor to keep the output voltage from
rising above 5% of its nominal value is found from:
R = 0.05 x 1.2V / 330 µA = 182Ω
A value of 120Ω is selected for the design example. This rep-
resents a 10 mA pre-load at the rated output voltage, which
is 0.01% of the 100A full load current.
CONTROL LOOP COMPENSATION
The LM3753 uses voltage-mode PWM control to correct
changes in output voltage due to line and load transients. In-
put voltage feed-forward is used to adjust the amplitude of the
PWM ramp. This stabilizes the modulator gain from variations
due to input voltage, providing a robust design solution. A fast
inner current sharing circuit ensures good dynamic response
to changes in load current.
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