LM3753 Datasheet, PDF (29/38 Pages) National Semiconductor (TI) – Scalable 2-Phase Synchronous Buck Controllers with Integrated FET Drivers and Linear Regulator Controller

and output inductor to avoid stray coupling. If possible, the
SNSP and SNSM traces should be shielded from the switch
node by ground planes.
SGND and PGND CONNECTIONS
Good layout techniques include a dedicated ground plane,
usually on an internal layer adjacent to the LM3753/54 and
signal component side of the board. Signal level components
connected to FB, TRACK/SS, FREQ, IAVE, EN and PH along
with the VCC and VIN bypass capacitors should be tied di-
rectly to the SGND pin. Connect the SGND and PGND pins
directly to the DAP, with vias from the DAP to the ground
plane. The ground plane is then connected to the input ca-
pacitors and low-side MOSFET source at each phase.
MINIMIZE the SWITCH NODE
The copper area that connects the power MOSFETs and out-
put inductor together radiates more EMI as it gets larger. Use
just enough copper to give low impedance for the switching
currents and provide adequate heat spreading for the MOS-
FETs.
LOW IMPEDANCE POWER PATH
In a buck regulator the primary switching loop consists of the
input capacitor connection to the MOSFETs. Minimizing the
area of this loop reduces the stray inductance, which mini-
mizes noise and possible erratic operation. The ceramic input
capacitors at each phase should be placed as close as pos-
sible to the MOSFETs, with the VIN side of the capacitors
connected directly to the high-side MOSFET drain, and the
PGND side of the capacitors connected as close as possible
to the low-side source. The complete power path includes the
input capacitors, power MOSFETs, output inductor, and out-
put capacitors. Keep these components on the same side of
the board and connect them with thick traces or copper
planes. Avoid connecting these components through vias
whenever possible, as vias add inductance and resistance. In
general, the power components should be kept close togeth-
er, minimizing the circuit board losses.
Comprehensive Equations
POWER STAGE TRANSFER FUNCTION
To include all terms, it is easiest to use the impedance form
of the equation:
ERROR AMPLIFIER TRANSFER FUNCTION
Using a single-pole operational amplifier model, the complete
error amplifier transfer function is given by:
Where the open loop gain A_OL = 3162 (70 dB) and the unity
gain bandwidth ω_BW = 2 x π x f_BW.
The ideal transfer function is expressed in terms of the mid-
band gain as:
The feedback gain is then:
Where:
Where:
With:
ERROR AMPLIFIER BANDWIDTH LIMIT
When the ideal error amplifier gain reaches the open loop
gain-bandwidth limit, the phase goes to zero. To incorporate
the amplifier bandwidth into the design procedure, determine
the boundary limit with respect to the ESR zero frequency:
Based on the relative ESR zero, the crossover frequency is
set at 1/3 of the bandwidth limiting frequency.
If ω_Z > ω_ZB, calculate the optimal crossover frequency from:
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