LM3753 Datasheet, PDF (17/38 Pages) National Semiconductor (TI) – Scalable 2-Phase Synchronous Buck Controllers with Integrated FET Drivers and Linear Regulator Controller

The restart after fault process for the LM3754 is the same as
the initial startup process. SS is pulled low and the system will
go through a full soft-start cycle. Switching will resume when
SS crosses above FB.
The restart after fault for the LM3753 is different from the initial
startup. When an over-current fault occurs, TRACK is usually
above VREF. In order to avoid V_OUT slewing up precipitously,
a fixed time internal soft-start is connected to the error ampli-
fier to control the rise of V_OUT. The low-side switch is not
turned on until the internal SS exceeds FB or VREF, which
allows V_OUT to remain high. The error amp will use as a ref-
erence the minimum of VREF, TRACK or the internal SS.
Once switching ensues a gradual transition to fully syn-
chronous operation occurs.
Over-voltage faults are only recognized by the Master con-
troller. About 5 µs after FB crosses above the OVP threshold,
which is 30% above VREF, the Master controller declares an
over-voltage fault. It pulls the FAULT bus low and all of the
controllers stop switching, with HG being low and LG being
high. The low-side MOSFETs pull V_OUT down to remove the
over-voltage condition. As soon as FB crosses below the un-
der-voltage detect point, which is 20% below VREF, the LG
outputs go low to turn off the low-side MOSFETs. This pre-
vents the negative inductor current from ramping too high.
The Master controller then waits 2 ms to allow any negative
inductor current to transition into the high-side MOSFETs
body diodes.
The restart from an over-voltage fault is the same as the
restart from an over-current fault. In addition there is an over-
voltage fault counter. On the seventh over-voltage fault, the
system does not restart. It waits for power or EN to be cycled.
This counter is reset to zero when power goes low or EN
crosses below its threshold.
PGOOD and PGOOD DELAY
PGOOD is an open-drain logic output. It is asserted HIGH
when the output voltage level is within the PGOOD window,
which is typically −20% to +30%. In order to operate, the
PGOOD output requires a pull-up resistor to an appropriate
supply voltage. This voltage is typically the supply for an ex-
ternal monitoring circuit. The resistor is selected so that it
limits the PGOOD sink current to less than 4 mA.
PGOOD is delayed from either power-up or VIN under-volt-
age lockout, and has three primary factors:
1) A synchronization delay, set to 2 ms after the slowest
controller in the system recognizes a valid level on EN, VCC
and VDD. This delay is timed out internally and allows for the
phase lock loops to synchronize.
2) Soft-Start/Track up, in non-fault conditions.
3) Transition period from diode emulation mode to fully
synchronous operation, set to 2 ms.
CURRENT SENSE and CURRENT LIMIT
The LM3753/54 senses current to enforce equal current shar-
ing and to protect against over-current faults. There are two
system options for sensing current; a current-sense resistor,
or a DCR configuration which uses the DC resistance of the
inductor. The current-sense resistor is more accurate but less
efficient than the DCR configuration.
The input range of the differential current-sense signal (CS1
(2) – CSM) is from −15 mV to +40 mV. The common mode
range is the same as the controller’s output range which is 0V
to 3.6V. Two considerations determine the value of the cur-
rent-sense resistor. If the resistor is too large there is an
efficiency loss. If it is too small the current-sense signal to the
controller will be too low. Choose a resistor that gives a full
load current-sense signal of at least 25 mV. This is typically
a resistor in the 1 mΩ to 2 mΩ range. The current-sense re-
sistor is inserted between the inductor and the load. The load
side of the resistor which is V_OUT, is connected to CSM, the
negative current-sense input. This is the negative current-
sense reference for both phases. The positive side of the
current-sense resistor goes to CS1(2).
For the DCR configuration a series resistor-capacitor combi-
nation is substituted for the current-sense resistor. The resis-
tor connects to the switch node (SW) and the capacitor
connects to V_OUT. CSM is connected to V_OUT as with the
sense resistor. CS1(2) is connected to the center point of the
resistor and capacitor, so that the current-sense signal is de-
veloped across the capacitor. The voltage across the capac-
itor is a low pass filtered version of the voltage across the
resistor-capacitor combination, in the same way the current
through the inductor is a low pass filtered version of the volt-
age applied across the inductor and its intrinsic series resis-
tance. Choose the DCR time constant (R_DCR x C_DCR) to be
1.0 to 1.5 times the inductor time constant (L / R_L). R_DCR is
selected so that the CS pin input bias current times R_DCR does
not cause a significant change in the CS voltage. The inductor
time constant and the DCR time constant will skew over tem-
perature since the components have different temperature
coefficients. Critical applications may employ a correction cir-
cuit based on a positive temperature coefficient thermistor
(PTC).
The over-current limit is set by placing a resistor between ILIM
and CSM. The value of the resistor times the ILIM current of
94 µA sets the over-current limit.
CURRENT SHARING and CURRENT AVERAGING
The current sharing works by adjusting the duty cycle of each
phase up or down to make the phase current equal to the
average current. The maximum duty cycle shift is ±20%.
To determine the average current, each phase sources a cur-
rent onto the IAVE bus proportional to its load current as
measured by the current sense amplifier connected to the
CS1(2) and CSM pins. The IAVE pins of all controllers are
connected together and a resistance of 8 kΩ per phase (par-
allel) to SGND provides the proper voltage level for the IAVE
bus. Each phase compares its current sense output to the
IAVE bus and sums the resultant voltage into the common
COMP signal to adjust the duty cycle for optimum current
sharing.
IAVE forms the current sharing bus for the entire power con-
verter. The IAVE pins of all controllers must be connected
together. Filter capacitors with a time constant of R_AV x C_AV =
1 / f_SW are connected between IAVE and SGND of each con-
troller. The parallel combination of the filter capacitors times
the summing resistors (one set per controller) forms the time
constant of the current sharing bus.
ERROR AMPLIFIER and LOOP COMPENSATION
The LM3753/54 uses a voltage mode PWM control method.
This requires a TYPE III or 3 pole, 2 zero compensation for
optimum bandwidth and stability. The error amplifier is a volt-
age type operational amplifier with 70 dB open loop gain and
unity gain bandwidth of 15 MHz. This allows for sufficient
phase boost at high control loop frequencies without degrad-
ing the error amplifier performance.
The error amplifier output COMP connections are different for
Master and Slave controllers. For the Master, a compensation
network is placed between the COMP pin and the FB pin. The
COMP pin of the Master is connected to the SNSP pin of each
Slave. The SNSM pin of each Slave is connected to the bot-
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