LM3753 Datasheet, PDF (21/38 Pages) National Semiconductor (TI) – Scalable 2-Phase Synchronous Buck Controllers with Integrated FET Drivers and Linear Regulator Controller

From the equation for V_P, the minimum value of C_O is:
For D < 0.5, V_L = V_OUT
For D > 0.5, V_L = V_IN − V_OUT
With R_C = V_P / ΔI_O this reduces to:
30091936
FIGURE 11. Multi-Phase Output Voltage Ripple
Based on the normalized single phase ripple, the worst case
multi-phase output voltage ripple can be approximated as:
ΔV_O(N) = ΔV_O / N
Where N is the number of phases.
The output capacitor selection will also affect the output volt-
age droop and overshoot during a load transient. The peak
transient of the output voltage during a load current step is
dependent on many factors. Given sufficient control loop
bandwidth an approximation of the transient voltage can be
obtained from:
With all values normalized to a single phase, V_P (V) is the
output voltage transient and ΔI_O (A) is the load current step
change. C_O (F) is the output capacitance, L (H) is the value
of the inductor and R_C (Ω) is the series resistance of the output
capacitor. V_L (V) is the minimum inductor voltage, which is
duty cycle dependent.
For D < 0.5, V_L = V_OUT
For D > 0.5, V_L = V_IN − V_OUT
This shows that as the input voltage approaches V_OUT, the
transient droop will get worse. The recovery overshoot re-
mains fairly constant.
The loss associated with the output capacitor series resis-
tance can be estimated as:
With R_C = 0 this reduces to:
Since D < 0.5, V_L = V_OUT. With R_C = 3 mΩ, the minimum value
for C_O is 476 μF.
The minimum control loop bandwidth f_C is given by:
For the design example, the minimum value for f_C is 44 kHz.
Two 220 μF, 5 mΩ polymer capacitors in parallel with two 22
μF, 3 mΩ ceramics per phase will meet the target output volt-
age ripple and transient specification.
INPUT CAPACITORS
The input capacitors for a buck regulator are used to smooth
the large current pulses drawn by the inductor and load when
the high-side MOSFET is on. Due to this large ac stress, input
capacitors are usually selected on the basis of their ac rms
current rating rather than bulk capacitance. Low ESR is ben-
eficial because it reduces the power dissipation in the capac-
itors. Although any of the capacitor types mentioned in the
OUTPUT CAPACITORS section can be used, ceramic ca-
pacitors are common because of their low series resistance.
In general the input to a buck converter does not require as
much bulk capacitance as the output.
The input capacitors should be selected for rms current rating
and minimum ripple voltage. The equation for the rms current
and power loss of the input capacitor in a single phase can
be estimated as:
Output Capacitor Design Procedure
For the design example V_IN = 12V, V_OUT = 1.2V, D = V_OUT /
V_IN = 0.1, L = 440 nH, ΔI_L = 9A, ΔI_O = 20A and V_P = 0.12V.
To meet the transient voltage specification, the maximum
R_C is:
For the design example, the maximum R_C is 6 mΩ. Choose
R_C = 3 mΩ as the design limit.
Where I_O (A) is the output load current and R_CIN (Ω) is the
series resistance of the input capacitor. Since the maximum
values occur at D = 0.5, a good estimate of the input capacitor
rms current rating in a single phase is one-half of the maxi-
mum output current.
Neglecting the series inductance of the input capacitance, the
input voltage ripple for a single phase can be estimated as:
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