LM3753 Datasheet, PDF (16/38 Pages) National Semiconductor (TI) – Scalable 2-Phase Synchronous Buck Controllers with Integrated FET Drivers and Linear Regulator Controller

pin. By means of the closed loop regulation through the
switching stage, FB will be regulated to TRACK. When
TRACK is below VREF, the LM3753 will control FB both up
and down to follow TRACK. When TRACK is above VREF,
FB will be regulated to VREF. A pre-biased output will be
pulled down by the LM3753. Full synchronous switching is
always employed on the LM3753, except for restart after a
fault condition.
When the LM3753 is ready to switch, normally TRACK will be
grounded and COMP will be low. LG will get pulled to VDD to
turn on the synchronous switch. As TRACK slews above FB,
COMP will slew up and LG will go high for 300 ns to charge
the HG bootstrap capacitor. Following this HG begins switch-
ing. COMP will set the duty cycle with normal PWM control of
HG and LG. The loop acts to have FB follow TRACK. If
V_OUT is too high, it will get pulled down. An internal timer sets
a 2 ms delay from the time of the first HG pulse, which occurs
as soon as COMP slews above the PWM ramp bottom.
When the 2 ms times out, PGOOD goes high if FB is above
the output under-voltage threshold on the Master, TRACK is
above VREF, no fault conditions are present, and SYNC is
toggling on the Slaves.
SOFT-START (LM3754)
The LM3754 implements a soft-start function, and operates
so as to prevent discharge of a pre-biased output. The error
amplifier amplifies the minimum of VREF or SS at the FB pin.
By means of the closed loop regulation through the switching
stage, FB will be regulated to SS. The Master controller
sources 10 µA onto the SS pin, while the Slaves do not source
any current. This sets the total soft-start current in a multi-
controller system to 10 µA.
The SS pin is automatically pulled down to SGND prior to the
onset of switching and during a restart from a fault condition.
When SS is initially released, COMP is low and no switching
occurs. Both LG and HG are held low while SS is below FB,
which guarantees that a pre-biased load will not be pulled
down. When SS crosses above either FB or VREF, COMP
will slew up and switching will start. The first switching pulse
is a 300 ns LG pulse to charge the external HG bootstrap
capacitor. After this the LG pulse width is reduced to zero.
This insures that V_OUT does not get pulled down while COMP
slews up and the system loop is settling. Pulses on HG cause
the high-side FET to turn-on so that FB tracks the SS pin as
it slews up. During the switch cycle off-time the inductor cur-
rent can only flow through the body diode of the synchronous
switch. During each successive cycle the LG pulse width
gradually increases. Over the course of 0.3 ms to 2.0 ms, de-
pending on the amount of pre-bias, LG pulses get longer until
full synchronous switching occurs. The internal timer waits 2
ms, regardless of duty cycle, for this transition in LG pulse
width to complete.
Following this PGOOD goes high if FB is above the output
under-voltage threshold on the Master, SS is above VREF,
no fault conditions are present, and SYNC is toggling on the
Slaves.
PHASE NUMBER SELECTION
The voltage at the PH pin determines the phase shift between
the two phases of each controller and also the phase shift
between the SYNC and SYNCOUT pulses in a Master-Slave
configuration. This voltage is read at startup and the resulting
phase configuration saved. The PH pin should be connected
to the center of a resistor divider between VCC and SGND to
select and program the required number of phases and the
corresponding phase delays per Table 1. Each controller re-
quires the same resistor divider at the PH pin.
30091925
FIGURE 5. Phase Selection
TABLE 1. Phase Divider Resistors
Number Of Divide Ratio
Phases
Target
R_PH1
(± 1%)
R_PH2
(± 1%)
2 & 4 Phases 0.000
Omit
0
3 Phases
5 Phases
6 Phases
8 Phases
10 Phases
12 Phases
0.214
0.357
0.5
0.643
0.786
1
7870Ω
6490Ω
4990Ω
3570Ω
2150Ω
0
2150Ω
3570Ω
4990Ω
6490Ω
7870Ω
Omit
OVER-CURRENT and OVER-VOLTAGE FAULTS
If any controller experiences a fault condition, it will pull the
FAULT bus low and all of the controllers will stop switching.
From the time when EN is low to the point where FAULT rises,
both HG and LG are low so that the SW node of each phase
is floating. The FAULT input may be pulled low externally
through an open drain MOSFET to disable the system.
The LM3753/54 employs cycle-by-cycle current limiting. This
occurs on each phase for both Master and Slave controllers.
The current (that is the CS1(2) − CSM voltage) is continuously
compared to the over-current set point (ILIM − CSM). Any
time that the current-sense signal exceeds current limit, the
cycle is ended.
In order to determine that a current fault has occurred, each
controller counts the number of over-current pulses. When
the sum of the counts for phase 1 and phase 2 reaches 446
an over-current fault is declared. The counter is reset after 16
consecutive switching cycles with no over-current on either
phase.
There is a second method for achieving an over-current fault,
which is meant to react to heavy shorts on V_OUT. The Master
controller will determine that an over-current fault has oc-
curred after 7 over-current cycles if the voltage at the FB pin
is less than 50% of its target value. This feature is disabled
during startup. Since the Slave controllers do not see the FB
voltage, they cannot detect this type of fault.
Any controller which sees an over-current fault will respond
by pulling the FAULT bus low. All of the controllers will react
and stop switching. Both HG and LG on each phase will be
pulled low. The inductor current in each phase will decay
through the body diodes of the low-side switches. The con-
troller which recognized the over-current fault will hold
FAULT low for 6 ms, which determines the hiccup time. This
allows the energy stored in the inductors to dissipate. After
this, FAULT is released and all of the controllers will restart
together.
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