COP840CJ Datasheet, PDF (25/36 Pages) National Semiconductor (TI) – 8-Bit Microcontrollers with Multi-Input Wake-Up and Brown Out Detector

Instruction Set
REGISTER AND SYMBOL DEFINITIONS
Registers
A 8-bit Accumulator register
B 8-bit Address register
X 8-bit Address register
SP 8-bit Stack pointer register
PC 15-bit Program counter register
PU Upper 7 bits of PC
PL Lower 8 bits of PC
C 1-bit of PSW register for carry
HC 1-bit of PSW register for half carry
GIE 1-bit of PSW register for global interrupt enable
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
X
LD
LD
LD
X
X
LD
LD
LD
CLRA
INC
DEC
LAID
DCOR
RRC
SWAP
SC
RC
IFC
IFNC
JMPL
JMP
Instr
A, MemI
A, MemI
A, MemI
A, MemI
A, MemI
A, MemI
A, MemI
A, MemI
#
Reg
#, Mem
#, Mem
#, Mem
A, Mem
A, MemI
Mem, Imm
Reg, Imm
A, [B±]
A, [X±]
A, [B±]
A, [X±]
[B±], Imm
A
A
A
A
A
Function
Add
Add with carry
Subtract with carry
Logical AND
Logical OR
Logical Exclusive-OR
IF equal
IF greater than
IF B not equal
Decrement Reg., skip if zero
Set bit
Reset bit
If bit
Exchange A with memory
Load A with memory
Load Direct memory Immed.
Load Register memory Immed.
Exchange A with memory [B]
Exchange A with memory [X]
Load A with memory [B]
Load A with memory [X]
Load memory immediate
Clear A
Increment A
Decrement A
Load A indirect from ROM
Decimal Correct A
Rotate right through carry
Swap nibbles of A
Set C
Reset C
If C
If Not C
Jump absolute long
Jump absolute
JP
Addr.
Jump relative short
Symbols
[B] Memory indirectly addressed by B register
[X] Memory indirectly addressed by X register
MD Direct addressed memory
Mem Direct addressed memory, or [B]
MemI Direct addressed memory, [B], or Immediate data
Imm 8-bit Immediate data
Reg Register memory: addresses F0 to FF (Includes B,
X, and SP)
Bit Bit number (0 to 7)
← Loaded with
↔ Exchanged with
Register Operation
A ← A + MemI
A ← A + MemI + C, C ← Carry
A ← A + MemI +C, C ← Carry
A ← A and MemI
A ← A or MemI
A ← A xor MemI
Compare A and MemI, Do next if A = MemI
Compare A and MemI, Do next if A > MemI
Do next if lower 4 bits of B not = Imm
Reg ← Reg − 1, skip if Reg goes to 0
1 to Mem.bit (bit = 0 to 7 immediate)
0 to Mem.bit (bit = 0 to 7 immediate)
If Mem.bit is true, do next instruction
A ↔ Mem
A ← MemI
Mem ← Imm
Reg ← Imm
A ↔ [B] (B ← B±1)
A ↔ [X] (X ← X±1)
A ← [B] (B ← B±1)
A ← [X] (X ← X±1)
[B] ← Imm (B ← B±1)
A←0
A←A+1
A←A−1
A ← ROM(PU,A)
A ← BCD correction (follows ADC, SUBC)
C → A7 → … → A0 → C
A7 … A4 ↔ A3 … A0
C←1
C←0
If C is true, do next instruction
If C is not true, do next instruction
PC ← ii (ii = 15 bits, 0 to 32k)
PC11...PC0 ← i (i = 12 bits)
PC15...PC12 remain unchanged
PC ← PC + r (r is −31 to +32, not 1)
25
www.national.com