COP840CJ Datasheet, PDF (21/36 Pages) National Semiconductor (TI) – 8-Bit Microcontrollers with Multi-Input Wake-Up and Brown Out Detector

Comparator (Continued)
TABLE 8. DC and AC Characteristics (Note 18) 4V ≤ V_CC ≤ 6V, −40˚C ≤ T_A ≤ +85˚C
Parameters
Input Offset Voltage
Input Common Mode Voltage Range
Voltage Gain
DC Supply Current (when enabled)
Response Time
Conditions
0.4V < V_IN < V_CC −1.5V
V_CC = 6.0V
100 mV Overdrive
500 mV Overdrive
1000 mV Overdrive
Note 18: For comparator output current characteristics see L-Port specs.
Min
Typ
Max
±10
±25
0.4
V_CC −1.5
300k
250
60
100
140
80
125
165
135
215
300
Units
mV
V
V/V
µA
ns
Multi-Input Wake-Up
The Multi-Input Wake-Up feature is used to return (wake-up)
the device from the HALT mode. Figure 14 shows the
Multi-Input Wake-Up logic.
DS012851-27
FIGURE 14. Multi-Input Wake-Up Logic
This feature utilizes the L Port. The user selects which par-
ticular L port bit or combination of L Port bits will cause the
device to exit the HALT mode. Three 8-bit memory mapped
registers, Reg:WKEN, Reg:WKEDG, and Reg:WKPNDare
used in conjunction with the L port to implement the
Multi-Input Wake-Up feature.
All three registers Reg:WKEN, Reg:WKPND, and
Reg:WKEDG are read/write registers, and are cleared at re-
set, except WKPND. WKPND is unknown on reset.
The user can select whether the trigger condition on the se-
lected L Port pin is going to be either a positive edge (low to
high transition) or a negative edge (high to low transition).
This selection is made via the Reg:WKEDG, which is an 8-bit
control register with a bit assigned to each L Port pin. Setting
the control bit will select the trigger condition to be a negative
edge on that particular L Port pin. Resetting the bit selects
the trigger condition to be a positive edge. Changing an edge
select entails several steps in order to avoid a pseudo
wake-up condition as a result of the edge change. First, the
associated WKEN bit should be reset, followed by the edge
select change in WKEDG. Next, the associated WKPND bit
should be cleared, followed by the associated WKEN bit be-
ing re-enabled.
An example may serve to clarify this procedure. Suppose we
wish to change the edge select from positive (low going high)
to negative (high going low) for L port bit 5, where bit 5 has
previously been enabled for an input. The program would be
as follows:
RBIT 5,WKEN
SBIT 5,WKEDG
RBIT 5,WKPND
SBIT 5,WKEN
If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wake-Up, a safety proce-
dure should also be followed to avoid inherited pseudo
wake-up conditions. After the selected L port bits have been
changed from output to input but before the associated
WKEN bits are enabled, the associated edge select bits in
WKEDG should be set or reset for the desired edge selects,
followed by the associated WKPND bits being cleared. This
same procedure should be used following RESET, since the
L port inputs are left floating as a result of RESET.
The occurrence of the selected trigger condition for
Multi-Input Wake-Up is latched into a pending register called
Reg:WKPND. The respective bits of the WKPND register will
be set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since the Reg:WKPND is a
pending register for the occurrence of selected wake-up con-
ditions, the device will not enter the HALT mode if any
wake-up bit is both enabled and pending. Setting the G7
data bit under this condition will not allow the device to enter
the HALT mode. Consequently, the user has the responsibil-
ity of clearing the pending flags before attempting to enter
the HALT mode.
If a crystal oscillator is being used, the wake-up signal will
not start the chip running immediately since crystal oscilla-
tors have a finite start up time. The WATCHDOG timer pres-
caler generates a fixed delay to ensure that the oscillator has
indeed stabilized before allowing the device to execute in-
structions. In this case, upon detecting a valid wake-up sig-
nal only the oscillator circuitry and the WATCHDOG timer
are enabled. The WATCHDOG timer prescaler is loaded with
a value of FF Hex (256 counts) and is clocked from the t_C in-
struction cycle clock. The t_Cclock is derived dividing down
the oscillator clock by a factor of 10. A Schmitt trigger follow-
ing the CKI on-chip inverter ensures that the WATCHDOG
timer is clocked only when the oscillator has a sufficiently
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