COP840CJ Datasheet, PDF(17/36 Page) National Semiconductor (TI) – 8-Bit Microcontrollers with Multi-Input Wake-Up and Brown Out Detector

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COP840CJ Datasheet, PDF (17/36 Pages) National Semiconductor (TI) – 8-Bit Microcontrollers with Multi-Input Wake-Up and Brown Out Detector

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MICROWIRE/PLUS (Continued)

TABLE 5. Timer Operating Modes

CNTRL Bits

765

000

001

010

011

100

101

110

111

Operating Mode

External Counter W/Auto-Load Reg.

Not Allowed

Timer W/Auto-Load Reg.

Timer W/Auto-Load Reg./Toggle TIO Out

Timer W/Capture Register

T Interrupt

Timer Underflow

Not Allowed

Timer Underflow

TIO Pos. Edge

TIO Neg. Edge

Timer

Counter On

TIO Pos. Edge

Not Allowed

WATCHDOG

The device has an on board 8-bit WATCHDOG timer. The

timer contains an 8-bit READ/WRITE down counter clocked

by an 8-bit prescaler. Under software control the timer can

be dedicated for the WATCHDOG or used as a general pur-

pose counter. Figure 10 shows the WATCHDOG timer block

diagram.

MODE 1: WATCHDOG TIMER

The WATCHDOG is designed to detect user programs get-

ting stuck in infinite loops resulting in loss of program control

or ârunawayâ programs. The WATCHDOG can be enabled or

disabled (only once) after the device is reset as a result of

Brown Out reset or external reset. On power-up the WATCH-

DOG is disabled. The WATCHDOG is enabled by writing a 1

to WDREN bit (resides in WDREG register). Once enabled,

the user program should write periodically into the 8-bit

counter before the counter underflows. The 8-bit counter

(WDCNT) is memory mapped at address 0CE Hex. The

counter is loaded with n-1 to get n counts. The counter un-

derflow resets the device, but does not disable the WATCH-

DOG. Loading the 8-bit counter initializes the prescaler with

FF Hex and starts the prescaler/counter. Prescaler and

counter are stopped upon counter underflow. Prescaler and

counter are each loaded with FF Hex when the device goes

into the HALT mode. The prescaler is used for crystal/

resonator start-up when the device exits the HALT mode

through Multi-Input Wake-up. In this case, the prescaler/

counter contents are changed.

MODE 2: TIMER

In this mode, the prescaler/counter is used as a timer by

keeping the WDREN (WATCHDOG reset enable) bit at 0.

The counter underflow sets the WDUDF (underflow) bit and

the underflow does not reset the device. Loading the 8-bit

counter (load n-1 for n counts) sets the WDTEN bit (WATCH-

DOG Timer Enable) to â1â, loads the prescaler with FF, and

starts the timer. The counter underflow stops the timer. The

WDTEN bit serves as a start bit for the WATCHDOG timer.

This bit is set when the 8-bit counter is loaded by the user

program. The load could be as a result of WATCHDOG ser-

vice (WATCHDOG timer dedicated for WATCHDOG func-

tion) or write to the counter (WATCHDOG timer used as a

general purpose counter). The bit is cleared upon Brown Out

reset, WATCHDOG reset or external reset. The bit is not

memory mapped and is transparent to the user program.

Control/Status Bits

WDUDF: WATCHDOG Timer Underflow Bit

This bit resides in the CNTRL2 Register. The bit is set when

the WATCHDOG timer underflows. The underflow resets the

device if the WATCHDOG reset enable bit is set (WDREN =

1). Otherwise, WDUDF can be used as the timer underflow

flag. The bit is cleared upon Brown-Out reset, external reset,

load to the 8-bit counter, or going into the HALT mode. It is a

read only bit.

WDREN: WD Reset Enable

WDREN bit resides in a separate register (bit 0 of WDREG).

This bit enables the WATCHDOG timer to generate a reset.

The bit is cleared upon Brown Out reset, or external reset.

The bit under software control can be written to only once

(once written to, the hardware does not allow the bit to be

changed during program execution).

WDREN = 1 WATCHDOG reset is enabled

WDREN = 0 WATCHDOG reset is disabled.

Table 6 shows the impact of Brown Out Reset, WATCHDOG

Reset, and External Reset on the Control/Status bits.

TABLE 6. WATCHDOG Control/Status

Parameter

8-bit Prescaler

8-bit WD counter

WDREN bit

WDUDF bit

WDTEN Signal

HALT

MODE

Unchanged

Note 16: BOR is Brown Out Reset

Reset

Unchanged

EXT/BOR (Note 16)

Reset

Load

Counter

User Value

No effect

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